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| author | Cui,Lili <lili.cui@intel.com> | 2020-06-09 10:43:39 +0800 |
|---|---|---|
| committer | Cui,Lili <lili.cui@intel.com> | 2020-09-24 10:38:15 +0800 |
| commit | 81d54bb7aec30fa09ee564c9a51765dc7c019799 (patch) | |
| tree | c07124d5a8d2d6c9f4011f118afe10445ef2cc25 /opcodes/i386-dis.c | |
| parent | 7469ddd78f8a5adc46dd1a8f883a74066ae4185b (diff) | |
| download | fsf-binutils-gdb-81d54bb7aec30fa09ee564c9a51765dc7c019799.zip fsf-binutils-gdb-81d54bb7aec30fa09ee564c9a51765dc7c019799.tar.gz fsf-binutils-gdb-81d54bb7aec30fa09ee564c9a51765dc7c019799.tar.bz2 | |
Add support for Intel TDX instructions.
gas/
* NEWS: Add TDX.
* config/tc-i386.c (cpu_arch): Add .tdx.
(cpu_noarch): Likewise.
* doc/c-i386.texi: Document tdx.
* testsuite/gas/i386/i386.exp: Run tdx tests.
* testsuite/gas/i386/tdx.d: Likewise.
* testsuite/gas/i386/tdx.s: Likewise.
* testsuite/gas/i386/x86-64-tdx.d: Likewise.
* testsuite/gas/i386/x86-64-tdx.s: Likewise.
opcodes/
* i386-dis.c (enum): Add PREFIX_0F01_REG_1_RM_5,
PREFIX_0F01_REG_1_RM_6, PREFIX_0F01_REG_1_RM_7,
X86_64_0F01_REG_1_RM_5_P_2, X86_64_0F01_REG_1_RM_6_P_2,
X86_64_0F01_REG_1_RM_7_P_2.
(prefix_table): Likewise.
(x86_64_table): Likewise.
(rm_table): Likewise.
* i386-gen.c (cpu_flag_init): Add CPU_TDX_FLAGS
and CPU_ANY_TDX_FLAGS.
(cpu_flags): Add CpuTDX.
* i386-opc.h (enum): Add CpuTDX.
(i386_cpu_flags): Add cputdx.
* i386-opc.tbl: Add TDX insns.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
Diffstat (limited to 'opcodes/i386-dis.c')
| -rw-r--r-- | opcodes/i386-dis.c | 65 |
1 files changed, 61 insertions, 4 deletions
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c index 7c898eb..19daeb4 100644 --- a/opcodes/i386-dis.c +++ b/opcodes/i386-dis.c @@ -952,6 +952,10 @@ enum enum { PREFIX_90 = 0, + PREFIX_0F01_REG_1_RM_4, + PREFIX_0F01_REG_1_RM_5, + PREFIX_0F01_REG_1_RM_6, + PREFIX_0F01_REG_1_RM_7, PREFIX_0F01_REG_3_RM_1, PREFIX_0F01_REG_5_MOD_0, PREFIX_0F01_REG_5_MOD_3_RM_0, @@ -1175,6 +1179,9 @@ enum X86_64_EA, X86_64_0F01_REG_0, X86_64_0F01_REG_1, + X86_64_0F01_REG_1_RM_5_PREFIX_2, + X86_64_0F01_REG_1_RM_6_PREFIX_2, + X86_64_0F01_REG_1_RM_7_PREFIX_2, X86_64_0F01_REG_2, X86_64_0F01_REG_3, X86_64_0F24, @@ -3083,6 +3090,38 @@ static const struct dis386 prefix_table[][4] = { { NULL, { { NULL, 0 } }, PREFIX_IGNORED } }, + /* PREFIX_0F01_REG_1_RM_4 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { "tdcall", { Skip_MODRM }, 0 }, + { Bad_Opcode }, + }, + + /* PREFIX_0F01_REG_1_RM_5 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { X86_64_TABLE (X86_64_0F01_REG_1_RM_5_PREFIX_2) }, + { Bad_Opcode }, + }, + + /* PREFIX_0F01_REG_1_RM_6 */ + { + { Bad_Opcode }, + { Bad_Opcode }, + { X86_64_TABLE (X86_64_0F01_REG_1_RM_6_PREFIX_2) }, + { Bad_Opcode }, + }, + + /* PREFIX_0F01_REG_1_RM_7 */ + { + { "encls", { Skip_MODRM }, 0 }, + { Bad_Opcode }, + { X86_64_TABLE (X86_64_0F01_REG_1_RM_7_PREFIX_2) }, + { Bad_Opcode }, + }, + /* PREFIX_0F01_REG_3_RM_1 */ { { "vmmcall", { Skip_MODRM }, 0 }, @@ -4205,6 +4244,24 @@ static const struct dis386 x86_64_table[][2] = { { "sidt", { M }, 0 }, }, + /* X86_64_0F01_REG_1_RM_5_PREFIX_2 */ + { + { Bad_Opcode }, + { "seamret", { Skip_MODRM }, 0 }, + }, + + /* X86_64_0F01_REG_1_RM_6_PREFIX_2 */ + { + { Bad_Opcode }, + { "seamops", { Skip_MODRM }, 0 }, + }, + + /* X86_64_0F01_REG_1_RM_7_PREFIX_2 */ + { + { Bad_Opcode }, + { "seamcall", { Skip_MODRM }, 0 }, + }, + /* X86_64_0F01_REG_2 */ { { "lgdt{Q|Q}", { M }, 0 }, @@ -8784,10 +8841,10 @@ static const struct dis386 rm_table[][8] = { { "mwait", { { OP_Mwait, 0 } }, 0 }, { "clac", { Skip_MODRM }, 0 }, { "stac", { Skip_MODRM }, 0 }, - { Bad_Opcode }, - { Bad_Opcode }, - { Bad_Opcode }, - { "encls", { Skip_MODRM }, 0 }, + { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_4) }, + { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_5) }, + { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_6) }, + { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_7) }, }, { /* RM_0F01_REG_2 */ |