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| author | Mike Frysinger <vapier@gentoo.org> | 2010-09-22 20:37:25 +0000 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2010-09-22 20:37:25 +0000 |
| commit | 59a82d2333aec12b174ad37f2f385afbfe06cf45 (patch) | |
| tree | 7ad9710f89a2604ab319b90ab84167999ce98526 /opcodes/bfin-dis.c | |
| parent | 528c6277f7e06c1fb117ddc21ff8b518f2092358 (diff) | |
| download | fsf-binutils-gdb-59a82d2333aec12b174ad37f2f385afbfe06cf45.zip fsf-binutils-gdb-59a82d2333aec12b174ad37f2f385afbfe06cf45.tar.gz fsf-binutils-gdb-59a82d2333aec12b174ad37f2f385afbfe06cf45.tar.bz2 | |
opcodes: blackfin: fix decoding of LSHIFT insns
The Blackfin ISA does not have a "SHIFT" insn, it has either LSHIFT,
ASHIFT, or BXORSHIFT. So be specific when disassembling.
As fall out of this change, we need to update some assembler tests.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'opcodes/bfin-dis.c')
| -rw-r--r-- | opcodes/bfin-dis.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/opcodes/bfin-dis.c b/opcodes/bfin-dis.c index 2f77c61..00799d2 100644 --- a/opcodes/bfin-dis.c +++ b/opcodes/bfin-dis.c @@ -4054,7 +4054,7 @@ decode_dsp32shift_0 (TIword iw0, TIword iw1, disassemble_info *outf) else if (sop == 2 && sopcde == 2) { OUTS (outf, dregs (dst0)); - OUTS (outf, " = SHIFT "); + OUTS (outf, " = LSHIFT "); OUTS (outf, dregs (src1)); OUTS (outf, " BY "); OUTS (outf, dregs_lo (src0)); @@ -4070,7 +4070,7 @@ decode_dsp32shift_0 (TIword iw0, TIword iw1, disassemble_info *outf) else if (sop == 2 && sopcde == 1) { OUTS (outf, dregs (dst0)); - OUTS (outf, " = SHIFT "); + OUTS (outf, " = LSHIFT "); OUTS (outf, dregs (src1)); OUTS (outf, " BY "); OUTS (outf, dregs_lo (src0)); |