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| author | claziss <claziss@synopsys.com> | 2017-07-19 09:56:55 +0200 |
|---|---|---|
| committer | claziss <claziss@synopsys.com> | 2017-07-19 09:56:55 +0200 |
| commit | 70b448ba7c521d6e0881f38aaf20d330fe510716 (patch) | |
| tree | 1b7ea381697ee0c39929ec525590045f50898b4f /opcodes/arc-regs.h | |
| parent | 7179e0e6b2e0ed7b220af8836a88ef308faf5898 (diff) | |
| download | fsf-binutils-gdb-70b448ba7c521d6e0881f38aaf20d330fe510716.zip fsf-binutils-gdb-70b448ba7c521d6e0881f38aaf20d330fe510716.tar.gz fsf-binutils-gdb-70b448ba7c521d6e0881f38aaf20d330fe510716.tar.bz2 | |
[ARC] Add SecureShield AUX registers
Update auxiliary registers with SecureShield ones.
opcodes/
2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
* arc-regs.h (sec_stat): New aux register.
(aux_kernel_sp): Likewise.
(aux_sec_u_sp): Likewise.
(aux_sec_k_sp): Likewise.
(sec_vecbase_build): Likewise.
(nsc_table_top): Likewise.
(nsc_table_base): Likewise.
(ersec_stat): Likewise.
(aux_sec_except): Likewise.
Diffstat (limited to 'opcodes/arc-regs.h')
| -rw-r--r-- | opcodes/arc-regs.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/opcodes/arc-regs.h b/opcodes/arc-regs.h index 99c39a4..f82e815 100644 --- a/opcodes/arc-regs.h +++ b/opcodes/arc-regs.h @@ -31,6 +31,7 @@ DEF (0x6, ARC_OPCODE_ARCALL, NONE, pc) DEF (0x7, ARC_OPCODE_ARCALL, NONE, adcr) DEF (0x8, ARC_OPCODE_ARCALL, NONE, apcr) DEF (0x9, ARC_OPCODE_ARCALL, NONE, acr) +DEF (0x9, ARC_OPCODE_ARCv2EM, NONE, sec_stat) DEF (0xa, ARC_OPCODE_ARCALL, NONE, status32) DEF (0xb, ARC_OPCODE_ARC600, NONE, status32_l1) DEF (0xb, ARC_OPCODE_ARC700, NONE, status32_l1) @@ -87,9 +88,12 @@ DEF (0x35, ARC_OPCODE_NONE, NONE, mx1) DEF (0x36, ARC_OPCODE_NONE, NONE, my0) DEF (0x37, ARC_OPCODE_NONE, NONE, my1) DEF (0x38, ARC_OPCODE_NONE, NONE, xyconfig) +DEF (0x38, ARC_OPCODE_ARCv2EM, NONE, aux_kernel_sp) DEF (0x39, ARC_OPCODE_NONE, NONE, scratch_a) +DEF (0x39, ARC_OPCODE_ARCv2EM, NONE, aux_sec_u_sp) DEF (0x3a, ARC_OPCODE_NONE, NONE, burstsys) DEF (0x3a, ARC_OPCODE_NONE, NONE, tsch) +DEF (0x3a, ARC_OPCODE_ARCv2EM, NONE, aux_sec_k_sp) DEF (0x3b, ARC_OPCODE_NONE, NONE, burstxym) DEF (0x3c, ARC_OPCODE_NONE, NONE, burstsz) DEF (0x3d, ARC_OPCODE_NONE, NONE, burstval) @@ -134,6 +138,7 @@ DEF (0x6d, ARC_OPCODE_ARCALL, NONE, mpu_build) DEF (0x6e, ARC_OPCODE_ARCALL, NONE, rf_build) DEF (0x6f, ARC_OPCODE_ARCALL, NONE, mmu_build) DEF (0x70, ARC_OPCODE_ARCALL, NONE, aa2_build) +DEF (0x70, ARC_OPCODE_ARCv2EM, NONE, sec_vecbase_build) DEF (0x71, ARC_OPCODE_ARCALL, NONE, vecbase_build) DEF (0x72, ARC_OPCODE_ARCALL, NONE, d_cache_build) DEF (0x73, ARC_OPCODE_ARCALL, NONE, madi_build) @@ -258,6 +263,8 @@ DEF (0x234, ARC_OPCODE_ARCALL, NONE, ap_ac6) DEF (0x235, ARC_OPCODE_ARCALL, NONE, ap_amv7) DEF (0x236, ARC_OPCODE_ARCALL, NONE, ap_amm7) DEF (0x237, ARC_OPCODE_ARCALL, NONE, ap_ac7) +DEF (0x268, ARC_OPCODE_ARCv2EM, NONE, nsc_table_top) +DEF (0x269, ARC_OPCODE_ARCv2EM, NONE, nsc_table_base) DEF (0x278, ARC_OPCODE_ARCALL, NONE, pct_control) DEF (0x279, ARC_OPCODE_ARCALL, NONE, pct_bank) DEF (0x290, ARC_OPCODE_ARCV2, NONE, jli_base) @@ -283,6 +290,8 @@ DEF (0x403, ARC_OPCODE_ARCALL, NONE, ecr) DEF (0x404, ARC_OPCODE_ARCALL, NONE, efa) DEF (0x405, ARC_OPCODE_ARC700, NONE, tlbpd0) DEF (0x406, ARC_OPCODE_ARC700, NONE, tlbpd1) +DEF (0x406, ARC_OPCODE_ARCv2EM, NONE, ersec_stat) +DEF (0x407, ARC_OPCODE_ARCv2EM, NONE, aux_sec_except) DEF (0x407, ARC_OPCODE_ARC700, NONE, tlbindex) DEF (0x408, ARC_OPCODE_ARC700, NONE, tlbcommand) DEF (0x409, ARC_OPCODE_ARC700, NONE, pid) |