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| author | Claudiu Zissulescu <claziss@synopsys.com> | 2016-11-15 15:11:47 +0100 |
|---|---|---|
| committer | Claudiu Zissulescu <claziss@synopsys.com> | 2016-11-29 11:29:18 +0100 |
| commit | abe7c33b45288b407e6d001aad713183d4bab5c6 (patch) | |
| tree | a3dbd4094e3acef74967b4c48d839fba8c726b83 /opcodes/arc-dis.c | |
| parent | ee881e5d3312ea5396bddc37e8673b77bf549b4b (diff) | |
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[ARC] Add checking for LP_COUNT reg usage, improve error reporting.
gas/
2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
* config/tc-arc.c (find_opcode_match): New function argument
errmsg.
(assemble_tokens): Collect and report the eventual error message
found during opcode matching process.
* testsuite/gas/arc/lpcount-err.s: New file.
* testsuite/gas/arc/add_s-err.s: Update error message.
opcode/
2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
* arc-opc.c (insert_ra_chk): New function.
(insert_rb_chk): Likewise.
(insert_rad): Update text error message.
(insert_rcd): Likewise.
(insert_rhv2): Likewise.
(insert_r0): Likewise.
(insert_r1): Likewise.
(insert_r2): Likewise.
(insert_r3): Likewise.
(insert_sp): Likewise.
(insert_gp): Likewise.
(insert_pcl): Likewise.
(insert_blink): Likewise.
(insert_ilink1): Likewise.
(insert_ilink2): Likewise.
(insert_ras): Likewise.
(insert_rbs): Likewise.
(insert_rcs): Likewise.
(insert_simm3s): Likewise.
(insert_rrange): Likewise.
(insert_fpel): Likewise.
(insert_blinkel): Likewise.
(insert_pcel): Likewise.
(insert_nps_3bit_dst): Likewise.
(insert_nps_3bit_dst_short): Likewise.
(insert_nps_3bit_src2_short): Likewise.
(insert_nps_bitop_size_2b): Likewise.
(MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Likewise.
(RA_CHK): Define.
(RB): Adjust.
(RB_CHK): Define.
(RC): Adjust.
* arc-dis.c (print_insn_arc): Add LOAD and STORE class.
* arc-tbl.h (div, divu): All instructions are DIVREM class.
Change first insn argument to check for LP_COUNT usage.
(rem): Likewise.
(ld, ldd): All instructions are LOAD class. Change first insn
argument to check for LP_COUNT usage.
(st, std): All instructions are STORE class.
(mac, mpy, dmac, mul, dmpy): All instructions are MPY class.
Change first insn argument to check for LP_COUNT usage.
(mov): All instructions are MOVE class. Change first insn
argument to check for LP_COUNT usage.
include/
2016-11-29 Claudiu Zissulescu <claziss@synopsys.com>
* opcode/arc.h (insn_class_t): Add DIVREM, LOAD, MOVE, MPY, STORE
instruction classes.
Diffstat (limited to 'opcodes/arc-dis.c')
| -rw-r--r-- | opcodes/arc-dis.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/opcodes/arc-dis.c b/opcodes/arc-dis.c index bcba2c7..77cf867 100644 --- a/opcodes/arc-dis.c +++ b/opcodes/arc-dis.c @@ -750,8 +750,10 @@ arc_opcode_to_insn_type (const struct arc_opcode *opcode) insn_type = dis_branch; } break; + case LOAD: + case STORE: case MEMORY: - insn_type = dis_dref; /* FIXME! DB indicates mov as memory! */ + insn_type = dis_dref; break; default: insn_type = dis_nonbranch; |