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| author | Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> | 2021-11-17 19:56:09 +0000 |
|---|---|---|
| committer | Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> | 2021-11-17 19:56:42 +0000 |
| commit | 1cad938de57a1577e5fe4b4afcabe889a8b9b9d7 (patch) | |
| tree | 0a83cfe3b99989bb705595bb9bf0855553e25e15 /opcodes/aarch64-tbl.h | |
| parent | 7bb5f07c8aa5168009f1e7b6857a30f0ee5ad16a (diff) | |
| download | fsf-binutils-gdb-1cad938de57a1577e5fe4b4afcabe889a8b9b9d7.zip fsf-binutils-gdb-1cad938de57a1577e5fe4b4afcabe889a8b9b9d7.tar.gz fsf-binutils-gdb-1cad938de57a1577e5fe4b4afcabe889a8b9b9d7.tar.bz2 | |
aarch64: [SME] Add ZERO instruction
This patch is adding ZERO (a list of 64-bit element ZA tiles)
instruction.
gas/ChangeLog:
* config/tc-aarch64.c (parse_sme_list_of_64bit_tiles):
New parser.
(parse_operands): Handle OPND_SME_list_of_64bit_tiles.
* testsuite/gas/aarch64/sme-4-illegal.d: New test.
* testsuite/gas/aarch64/sme-4-illegal.l: New test.
* testsuite/gas/aarch64/sme-4-illegal.s: New test.
* testsuite/gas/aarch64/sme-4.d: New test.
* testsuite/gas/aarch64/sme-4.s: New test.
include/ChangeLog:
* opcode/aarch64.h (enum aarch64_opnd): New operand
AARCH64_OPND_SME_list_of_64bit_tiles.
opcodes/ChangeLog:
* aarch64-opc.c (print_sme_za_list): New printing function.
(aarch64_print_operand): Handle OPND_SME_list_of_64bit_tiles.
* aarch64-opc.h (enum aarch64_field_kind): New bitfield
FLD_SME_zero_mask.
* aarch64-tbl.h (struct aarch64_opcode): New ZERO instruction.
aarch64-asm-2.c: Regenerate.
aarch64-dis-2.c: Regenerate.
aarch64-opc-2.c: Regenerate.
Diffstat (limited to 'opcodes/aarch64-tbl.h')
| -rw-r--r-- | opcodes/aarch64-tbl.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 5307cda..9313220 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -5136,6 +5136,8 @@ const struct aarch64_opcode aarch64_opcode_table[] = SME_INSN ("mova", 0xc0020000, 0xff3e0200, sme_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SME_ZA_HV_idx_src), OP_SME_BHSDQ_PM_BHSDQ, 0, 0), SME_INSN ("mova", 0xc0000000, 0xff3e0010, sme_misc, 0, OP3 (SME_ZA_HV_idx_dest, SVE_Pg3, SVE_Zn), OP_SME_BHSDQ_PM_BHSDQ, 0, 0), + SME_INSN ("zero", 0xc0080000, 0xffffff00, sme_misc, 0, OP1 (SME_list_of_64bit_tiles), {}, 0, 0), + /* SIMD Dot Product (optional in v8.2-A). */ DOT_INSN ("udot", 0x2e009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ), DOT_INSN ("sdot", 0xe009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ), @@ -5715,6 +5717,8 @@ const struct aarch64_opcode aarch64_opcode_table[] = "an SME horizontal or vertical vector access register") \ Y(PRED_REG, regno, "SME_Pm", 0, F(FLD_SME_Pm), \ "an SVE predicate register") \ + Y(SVE_REG, imm, "SME_list_of_64bit_tiles", 0, \ + F(FLD_SME_zero_mask), "list of 64-bit ZA element tiles") \ Y(IMMEDIATE, imm, "TME_UIMM16", 0, F(FLD_imm16), \ "a 16-bit unsigned immediate for TME tcancel") \ Y(SIMD_ELEMENT, reglane, "SM3_IMM2", 0, F(FLD_SM3_imm2), \ |