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| author | Jiong Wang <jiong.wang@arm.com> | 2014-09-03 14:45:26 +0100 |
|---|---|---|
| committer | Jiong Wang <jiong.wang@arm.com> | 2014-09-03 14:53:53 +0100 |
| commit | df7b4545b2b49572ab63690c130df973af109615 (patch) | |
| tree | 49bdec91dcec920e99e5e3fd36fdc6c413d56e24 /opcodes/aarch64-tbl.h | |
| parent | ee804238f097e91088a340c15891170f2748b4fd (diff) | |
| download | fsf-binutils-gdb-df7b4545b2b49572ab63690c130df973af109615.zip fsf-binutils-gdb-df7b4545b2b49572ab63690c130df973af109615.tar.gz fsf-binutils-gdb-df7b4545b2b49572ab63690c130df973af109615.tar.bz2 | |
[PATCH/AArch64] Generic support for all system registers using mrs and msr
2014-09-03 Jiong Wang <jiong.wang@arm.com>
opcode/
* aarch64-tbl.h (aarch64_opcode_table): Update encoding for mrs/msr.
* aarch64-dis-2.c: Update auto-generated file.
gas/
* config/tc-aarch64.c (parse_sys_reg): Remove the restriction on op0 field.
gas/testsuite/
* gas/aarch64/illegal.s: Update testcase.
* gas/aarch64/illegal.d: Likewise.
* gas/aarch64/sysreg-1.s: Likewise.
* gas/aarch64/sysreg-1.d: Likewise.
Diffstat (limited to 'opcodes/aarch64-tbl.h')
| -rw-r--r-- | opcodes/aarch64-tbl.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 13a205f..1a16656 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -2272,9 +2272,9 @@ struct aarch64_opcode aarch64_opcode_table[] = {"dc", 0xd5080000, 0xfff80000, ic_system, 0, CORE, OP2 (SYSREG_DC, Rt), QL_SRC_X, F_ALIAS}, {"ic", 0xd5080000, 0xfff80000, ic_system, 0, CORE, OP2 (SYSREG_IC, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)}, {"tlbi", 0xd5080000, 0xfff80000, ic_system, 0, CORE, OP2 (SYSREG_TLBI, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)}, - {"msr", 0xd5100000, 0xfff00000, ic_system, 0, CORE, OP2 (SYSREG, Rt), QL_SRC_X, 0}, + {"msr", 0xd5000000, 0xffe00000, ic_system, 0, CORE, OP2 (SYSREG, Rt), QL_SRC_X, 0}, {"sysl", 0xd5280000, 0xfff80000, ic_system, 0, CORE, OP5 (Rt, UIMM3_OP1, Cn, Cm, UIMM3_OP2), QL_SYSL, 0}, - {"mrs", 0xd5300000, 0xfff00000, ic_system, 0, CORE, OP2 (Rt, SYSREG), QL_DST_X, 0}, + {"mrs", 0xd5200000, 0xffe00000, ic_system, 0, CORE, OP2 (Rt, SYSREG), QL_DST_X, 0}, /* Test & branch (immediate). */ {"tbz", 0x36000000, 0x7f000000, testbranch, 0, CORE, OP3 (Rt, BIT_NUM, ADDR_PCREL14), QL_PCREL_14, 0}, {"tbnz", 0x37000000, 0x7f000000, testbranch, 0, CORE, OP3 (Rt, BIT_NUM, ADDR_PCREL14), QL_PCREL_14, 0}, |