diff options
| author | Matthew Malcomson <matthew.malcomson@arm.com> | 2019-05-09 10:29:18 +0100 |
|---|---|---|
| committer | Matthew Malcomson <matthew.malcomson@arm.com> | 2019-05-09 10:29:18 +0100 |
| commit | c469c86473273e115b267a6f8c93c8942deb93c4 (patch) | |
| tree | 287fc69d0de95ceb865fef1bb99c4e1bd85b7ef8 /opcodes/aarch64-tbl.h | |
| parent | 116adc27470ed3682b6236e44e3b18838673036c (diff) | |
| download | fsf-binutils-gdb-c469c86473273e115b267a6f8c93c8942deb93c4.zip fsf-binutils-gdb-c469c86473273e115b267a6f8c93c8942deb93c4.tar.gz fsf-binutils-gdb-c469c86473273e115b267a6f8c93c8942deb93c4.tar.bz2 | |
[binutils][aarch64] New SVE_ADDR_ZX operand.
Add AARCH64_OPND_SVE_ADDR_ZX operand that allows a vector of addresses
in a Zn register, offset by an Xm register.
This is used with scatter/gather SVE2 instructions.
gas/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* config/tc-aarch64.c (REG_ZR): Macro specifying zero register.
(parse_address_main): Account for new addressing mode [Zn.S, Xm].
(parse_operands): Handle new SVE_ADDR_ZX operand.
include/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* opcode/aarch64.h (enum aarch64_opnd): New SVE_ADDR_ZX operand.
opcodes/ChangeLog:
2019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
* aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
for SVE_ADDR_ZX.
(aarch64_print_operand): Add printing for SVE_ADDR_ZX.
* aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
Diffstat (limited to 'opcodes/aarch64-tbl.h')
| -rw-r--r-- | opcodes/aarch64-tbl.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index d62c53b..ba5d6b5 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -4807,6 +4807,9 @@ struct aarch64_opcode aarch64_opcode_table[] = Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RX_LSL3", \ (3 << OPD_F_OD_LSB) | OPD_F_NO_ZR, F(FLD_Rn,FLD_Rm), \ "an address with a scalar register offset") \ + Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_ZX", \ + 0 << OPD_F_OD_LSB , F(FLD_SVE_Zn,FLD_Rm), \ + "vector of address with a scalar register offset") \ Y(ADDRESS, sve_addr_rr_lsl, "SVE_ADDR_RZ", 0 << OPD_F_OD_LSB, \ F(FLD_Rn,FLD_SVE_Zm_16), \ "an address with a vector register offset") \ |