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| author | Sudakshina Das <sudi.das@arm.com> | 2020-04-20 10:58:16 +0100 |
|---|---|---|
| committer | Sudakshina Das <sudi.das@arm.com> | 2020-04-20 10:58:16 +0100 |
| commit | c2e5c986b3825c16a578e5bf84aa412eec276dc7 (patch) | |
| tree | a3164a12168f5db7c0145d75fc0255a4de02bc23 /opcodes/aarch64-tbl.h | |
| parent | 8a6e1d1d7f2fb09245fe42f7b8dc6d53f61df1d1 (diff) | |
| download | fsf-binutils-gdb-c2e5c986b3825c16a578e5bf84aa412eec276dc7.zip fsf-binutils-gdb-c2e5c986b3825c16a578e5bf84aa412eec276dc7.tar.gz fsf-binutils-gdb-c2e5c986b3825c16a578e5bf84aa412eec276dc7.tar.bz2 | |
[AArch64, Binutils] Add missing TSB instruction
This patch implements the TSB instructions:
https://developer.arm.com/docs/ddi0596/f/base-instructions-alphabetic-order/
tsb-csync-trace-synchronization-barrier
Since TSB and PSB both use the same (and only) argument "CSYNC", this patch
reuses it for TSB. However, the same argument would imply different value
for CRm:Op2 which are anyway fixed values, so I have diverted the
inserter/extracter function to dummy versions instead of the "hint" version.
The operand checker part still uses the existing infratructure for
AARCH64_OPND_BARRIER_PSB to make sure the operand is parsed correctly.
gas/ChangeLog:
2020-04-20 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (parse_barrier_psb): Update error messages
to include TSB.
* testsuite/gas/aarch64/system-2.d: Update -march and new tsb tests.
* testsuite/gas/aarch64/system-2.s: Add new tsb tests.
* testsuite/gas/aarch64/system.d: Update.
opcodes/ChangeLog:
2020-04-20 Sudakshina Das <sudi.das@arm.com>
* aarch64-asm.c (aarch64_ins_none): New.
* aarch64-asm.h (ins_none): New declaration.
* aarch64-dis.c (aarch64_ext_none): New.
* aarch64-dis.h (ext_none): New declaration.
* aarch64-opc.c (aarch64_print_operand): Update case for
AARCH64_OPND_BARRIER_PSB.
* aarch64-tbl.h (aarch64_opcode_table): Add tsb.
(AARCH64_OPERANDS): Update inserter/extracter for
AARCH64_OPND_BARRIER_PSB to use new dummy functions.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
Diffstat (limited to 'opcodes/aarch64-tbl.h')
| -rw-r--r-- | opcodes/aarch64-tbl.h | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 3c3731d..46c0386 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -3841,6 +3841,7 @@ struct aarch64_opcode aarch64_opcode_table[] = CORE_INSN ("autib1716", 0xd50321df, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), CORE_INSN ("esb", 0xd503221f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), CORE_INSN ("psb", 0xd503223f, 0xffffffff, ic_system, 0, OP1 (BARRIER_PSB), {}, F_ALIAS), + CORE_INSN ("tsb", 0xd503225f, 0xffffffff, ic_system, 0, OP1 (BARRIER_PSB), {}, F_ALIAS), CORE_INSN ("clrex", 0xd503305f, 0xfffff0ff, ic_system, 0, OP1 (UIMM4), {}, F_OPD0_OPT | F_DEFAULT (0xF)), CORE_INSN ("dsb", 0xd503309f, 0xfffff0ff, ic_system, 0, OP1 (BARRIER), {}, F_HAS_ALIAS), CORE_INSN ("ssbb", 0xd503309f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), @@ -5314,8 +5315,8 @@ struct aarch64_opcode aarch64_opcode_table[] = "the ISB option name SY or an optional 4-bit unsigned immediate") \ Y(SYSTEM, prfop, "PRFOP", 0, F(), \ "a prefetch operation specifier") \ - Y(SYSTEM, hint, "BARRIER_PSB", 0, F (), \ - "the PSB option name CSYNC") \ + Y(SYSTEM, none, "BARRIER_PSB", 0, F (), \ + "the PSB/TSB option name CSYNC") \ Y(SYSTEM, hint, "BTI", 0, F (), \ "BTI targets j/c/jc") \ Y(ADDRESS, sve_addr_ri_s4, "SVE_ADDR_RI_S4x16", \ |