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| author | Victor Do Nascimento <victor.donascimento@arm.com> | 2024-01-04 13:34:52 +0000 |
|---|---|---|
| committer | Victor Do Nascimento <victor.donascimento@arm.com> | 2024-01-15 13:11:48 +0000 |
| commit | 9e263f69a77565aab4475bf6b984f09f2b0c6755 (patch) | |
| tree | d5b137280e7fdfb047bf8ffdb6852fc0604d219b /opcodes/aarch64-tbl.h | |
| parent | 907aee5baf05bf54faa950aba52ed09fc79085eb (diff) | |
| download | fsf-binutils-gdb-9e263f69a77565aab4475bf6b984f09f2b0c6755.zip fsf-binutils-gdb-9e263f69a77565aab4475bf6b984f09f2b0c6755.tar.gz fsf-binutils-gdb-9e263f69a77565aab4475bf6b984f09f2b0c6755.tar.bz2 | |
aarch64: rcpc3: Add +rcpc3 architectural feature support flag
Indicating the presence of the Armv8.2-a feature adding further
support for the Release Consistency Model, the `+rcpc3' architectural
extension flag is added to the list of possible `-march' options in
Binutils, together with the necessary macro for encoding rcpc3
instructions.
Diffstat (limited to 'opcodes/aarch64-tbl.h')
| -rw-r--r-- | opcodes/aarch64-tbl.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 128cbf5..149265a 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -2647,6 +2647,9 @@ static const aarch64_feature_set aarch64_feature_sme2p1 = AARCH64_FEATURE (SME2p1); static const aarch64_feature_set aarch64_feature_sve2p1 = AARCH64_FEATURE (SVE2p1); +static const aarch64_feature_set aarch64_feature_rcpc3 = + AARCH64_FEATURE (RCPC3); + #define CORE &aarch64_feature_v8 #define FP &aarch64_feature_fp @@ -2712,6 +2715,7 @@ static const aarch64_feature_set aarch64_feature_sve2p1 = #define B16B16 &aarch64_feature_b16b16 #define SME2p1 &aarch64_feature_sme2p1 #define SVE2p1 &aarch64_feature_sve2p1 +#define RCPC3 &aarch64_feature_rcpc3 #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL } |