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authorSrinath Parvathaneni <srinath.parvathaneni@arm.com>2024-02-29 21:06:25 +0000
committersrinath <srinath.parvathaneni@arm.com>2024-02-29 21:19:04 +0000
commit831be495ef18c2df5964fbd5dc7c6c16fc275d13 (patch)
tree66205699ef34147b2ab7c98b553aa8faece90e1f /opcodes/aarch64-tbl.h
parent9dce3449f5b003aa489b848fa436d39f1973f49e (diff)
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aarch64: Fix the 2nd operand in gcsstr and gcssttr instructions.
The assembler wrongly expects plain register name instead of memory-form 2nd operand for gcsstr and gcssttr instructions. This patch fixes the issue.
Diffstat (limited to 'opcodes/aarch64-tbl.h')
-rw-r--r--opcodes/aarch64-tbl.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 66d68c0..093eb60 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -4283,8 +4283,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
GCS_INSN ("gcsss2", 0xd52b7760, 0xffffffe0, OP1 (Rt), QL_I1X, 0),
GCS_INSN ("gcspopm", 0xd52b773f, 0xffffffff, OP0 (), {}, 0),
GCS_INSN ("gcspopm", 0xd52b7720, 0xffffffe0, OP1 (Rt), QL_I1X, 0),
- GCS_INSN ("gcsstr", 0xd91f0c00, 0xfffffc00, OP2 (Rt, Rn_SP), QL_I2SAMEX, 0),
- GCS_INSN ("gcssttr", 0xd91f1c00, 0xfffffc00, OP2 (Rt, Rn_SP), QL_I2SAMEX, 0),
+ GCS_INSN ("gcsstr", 0xd91f0c00, 0xfffffc00, OP2 (Rt, ADDR_SIMPLE), QL_DST_X, 0),
+ GCS_INSN ("gcssttr", 0xd91f1c00, 0xfffffc00, OP2 (Rt, ADDR_SIMPLE), QL_DST_X, 0),
CORE_INSN ("gcsb", 0xd503227f, 0xffffffff, ic_system, 0, OP1 (BARRIER_GCSB), {}, F_ALIAS),
CORE_INSN ("sys", 0xd5080000, 0xfff80000, ic_system, 0, OP5 (UIMM3_OP1, CRn, CRm, UIMM3_OP2, Rt), QL_SYS, F_HAS_ALIAS | F_OPD4_OPT | F_DEFAULT (0x1F)),
D128_INSN ("sysp", 0xd5480000, 0xfff80000, OP6 (UIMM3_OP1, CRn, CRm, UIMM3_OP2, Rt, PAIRREG_OR_XZR), QL_SYSP, F_HAS_ALIAS | F_OPD_NARROW | F_OPD4_OPT | F_OPD_PAIR_OPT | F_DEFAULT (0x1f)),