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| author | Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> | 2020-10-28 14:09:25 +0000 |
|---|---|---|
| committer | Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> | 2020-10-28 14:12:37 +0000 |
| commit | 82503ca7ed8301dc076919d5010bf981e35b1314 (patch) | |
| tree | 3edc543156ab0041ba79b4cb2c96ca685bbf135a /opcodes/aarch64-tbl.h | |
| parent | fd195909ce14c7e852319613e7ec6a9a6e7b99ea (diff) | |
| download | fsf-binutils-gdb-82503ca7ed8301dc076919d5010bf981e35b1314.zip fsf-binutils-gdb-82503ca7ed8301dc076919d5010bf981e35b1314.tar.gz fsf-binutils-gdb-82503ca7ed8301dc076919d5010bf981e35b1314.tar.bz2 | |
aarch64: Add WFET instruction for Armv8.7-a
This patch adds new to Armv8.7 WFET instruction which take one operand:
WFET <Xt>
Where:
<Xt> is 64-bit name of the general-purpose source register, encoded in the
"Rd" field.
For more details regarding WFET (Wait For Event with Timeout) instruction for
Armv8.7-a please refer to Arm A64 Instruction set documentation for Armv8-A
architecture profile, see document pages 565 of [0].
[0]: https://developer.arm.com/docs/ddi0596/i
gas/ChangeLog:
2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* NEWS: Update docs.
* testsuite/gas/aarch64/system-5.d: New test.
* testsuite/gas/aarch64/system-5.s: New test.
opcodes/ChangeLog:
2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* aarch64-tbl.h (struct aarch64_opcode): Add new WFET instruction encoding
and operand description.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
Diffstat (limited to 'opcodes/aarch64-tbl.h')
| -rw-r--r-- | opcodes/aarch64-tbl.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 119625a..a3014c1 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -3867,6 +3867,7 @@ struct aarch64_opcode aarch64_opcode_table[] = CORE_INSN ("dc", 0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_DC, Rt), QL_SRC_X, F_ALIAS), CORE_INSN ("ic", 0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_IC, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)), CORE_INSN ("tlbi",0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_TLBI, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)), + V8_7_INSN ("wfet", 0xd5031000, 0xffffffe0, ic_system, OP1 (Rd), QL_I1X, F_HAS_ALIAS), PREDRES_INSN ("cfp", 0xd50b7380, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS), PREDRES_INSN ("dvp", 0xd50b73a0, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS), PREDRES_INSN ("cpp", 0xd50b73e0, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS), |