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| author | Victor Do Nascimento <victor.donascimento@arm.com> | 2023-10-30 11:47:23 +0000 |
|---|---|---|
| committer | Victor Do Nascimento <victor.donascimento@arm.com> | 2023-11-07 21:53:59 +0000 |
| commit | 6219f9dae7d04b52ef171e0aa3341bf977b05a68 (patch) | |
| tree | d228c4c76f5941fbcfa736fcc3584f0d7d523893 /opcodes/aarch64-tbl.h | |
| parent | ecd4c78dddefe41d9fc7b947fdf4e76b743b2b02 (diff) | |
| download | fsf-binutils-gdb-6219f9dae7d04b52ef171e0aa3341bf977b05a68.zip fsf-binutils-gdb-6219f9dae7d04b52ef171e0aa3341bf977b05a68.tar.gz fsf-binutils-gdb-6219f9dae7d04b52ef171e0aa3341bf977b05a68.tar.bz2 | |
aarch64: Add LSE128 instruction operand support
Given the particular encoding of the LSE128 instructions, create the
necessary shared input+output operand register description and
handling in the code to allow for the encoding of the LSE128 128-bit
atomic operations.
gas/ChangeLog:
* config/tc-aarch64.c (parse_operands):
include/ChangeLog:
* opcode/aarch64.h (enum aarch64_opnd):
opcodes/ChangeLog:
* aarch64-opc.c (fields):
(aarch64_print_operand):
* aarch64-opc.h (enum aarch64_field_kind):
* aarch64-tbl.h (AARCH64_OPERANDS):
Diffstat (limited to 'opcodes/aarch64-tbl.h')
| -rw-r--r-- | opcodes/aarch64-tbl.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index e624b85..bc38542 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -6308,6 +6308,8 @@ const struct aarch64_opcode aarch64_opcode_table[] = "the GCSB option name DSYNC") \ Y(SYSTEM, hint, "BTI_TARGET", 0, F (), \ "BTI targets j/c/jc") \ + Y(INT_REG, regno, "LSE128_Rt", 0, F(FLD_LSE128_Rt), "an integer register") \ + Y(INT_REG, regno, "LSE128_Rt2", 0, F(FLD_LSE128_Rt2), "an integer register") \ Y(ADDRESS, sve_addr_ri_s4, "SVE_ADDR_RI_S4x16", \ 4 << OPD_F_OD_LSB, F(FLD_Rn), \ "an address with a 4-bit signed offset, multiplied by 16") \ |