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| author | Andrew Carlotti <andrew.carlotti@arm.com> | 2024-01-12 01:44:46 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2024-01-12 13:46:35 +0000 |
| commit | 59255bf7d20f78f540b2f0016c29fc1e8d614f1b (patch) | |
| tree | 5505b7db460804f7d8de126dd0f508c2891361f4 /opcodes/aarch64-tbl.h | |
| parent | 368910707c60c2008cf241959caec68968ea78ed (diff) | |
| download | fsf-binutils-gdb-59255bf7d20f78f540b2f0016c29fc1e8d614f1b.zip fsf-binutils-gdb-59255bf7d20f78f540b2f0016c29fc1e8d614f1b.tar.gz fsf-binutils-gdb-59255bf7d20f78f540b2f0016c29fc1e8d614f1b.tar.bz2 | |
aarch64: Add +wfxt flag for existing instructions
Diffstat (limited to 'opcodes/aarch64-tbl.h')
| -rw-r--r-- | opcodes/aarch64-tbl.h | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 1838f99..f6538aa 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -2598,6 +2598,8 @@ static const aarch64_feature_set aarch64_feature_ls64 = AARCH64_FEATURE (LS64); static const aarch64_feature_set aarch64_feature_flagm = AARCH64_FEATURE (FLAGM); +static const aarch64_feature_set aarch64_feature_wfxt = + AARCH64_FEATURE (WFXT); static const aarch64_feature_set aarch64_feature_mops = AARCH64_FEATURE (MOPS); static const aarch64_feature_set aarch64_feature_mops_memtag = @@ -2676,6 +2678,7 @@ static const aarch64_feature_set aarch64_feature_d128_the = #define ARMV8_7A &aarch64_feature_v8_7a #define LS64 &aarch64_feature_ls64 #define FLAGM &aarch64_feature_flagm +#define WFXT &aarch64_feature_wfxt #define MOPS &aarch64_feature_mops #define MOPS_MEMTAG &aarch64_feature_mops_memtag #define HBC &aarch64_feature_hbc @@ -2825,6 +2828,8 @@ static const aarch64_feature_set aarch64_feature_d128_the = { NAME, OPCODE, MASK, CLASS, 0, ARMV8R, OPS, QUALS, FLAGS, 0, 0, NULL } #define V8_7A_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, ARMV8_7A, OPS, QUALS, FLAGS, 0, 0, NULL } +#define WFXT_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ + { NAME, OPCODE, MASK, CLASS, 0, WFXT, OPS, QUALS, FLAGS, 0, 0, NULL } #define _LS64_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, LS64, OPS, QUALS, FLAGS, 0, 0, NULL } #define FLAGM_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ @@ -4245,8 +4250,8 @@ const struct aarch64_opcode aarch64_opcode_table[] = CORE_INSN ("ic", 0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_IC, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)), CORE_INSN ("tlbi",0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_TLBI, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)), D128_INSN ("tlbip",0xd5480000, 0xfff80000, OP3 (SYSREG_TLBIP, Rt_SYS, PAIRREG_OR_XZR), QL_SRC_X2, F_ALIAS| F_OPD1_OPT | F_OPD_PAIR_OPT | F_DEFAULT (0x1f)), - V8_7A_INSN ("wfet", 0xd5031000, 0xffffffe0, ic_system, OP1 (Rd), QL_I1X, F_HAS_ALIAS), - V8_7A_INSN ("wfit", 0xd5031020, 0xffffffe0, ic_system, OP1 (Rd), QL_I1X, F_HAS_ALIAS), + WFXT_INSN ("wfet", 0xd5031000, 0xffffffe0, ic_system, OP1 (Rd), QL_I1X, F_HAS_ALIAS), + WFXT_INSN ("wfit", 0xd5031020, 0xffffffe0, ic_system, OP1 (Rd), QL_I1X, F_HAS_ALIAS), PREDRES_INSN ("cfp", 0xd50b7380, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS), PREDRES_INSN ("dvp", 0xd50b73a0, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS), PREDRES_INSN ("cpp", 0xd50b73e0, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS), |