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| author | Victor Do Nascimento <victor.donascimento@arm.com> | 2024-01-05 17:26:09 +0000 |
|---|---|---|
| committer | Victor Do Nascimento <victor.donascimento@arm.com> | 2024-01-15 13:11:48 +0000 |
| commit | 51bb8593e6f533970385ca64f40a5bbfc82285da (patch) | |
| tree | 4f3c00dfd49d72c17c344221c2cff2accdf1d31e /opcodes/aarch64-tbl.h | |
| parent | c35460087723932ba7300072099bd0d65d9ce6d2 (diff) | |
| download | fsf-binutils-gdb-51bb8593e6f533970385ca64f40a5bbfc82285da.zip fsf-binutils-gdb-51bb8593e6f533970385ca64f40a5bbfc82285da.tar.gz fsf-binutils-gdb-51bb8593e6f533970385ca64f40a5bbfc82285da.tar.bz2 | |
aarch64: rcpc3: New RCPC3_ADDR operand types
The particular choices of address indexing, along with their encoding
for RCPC3 instructions lead to the requirement of a new set of operand
descriptions, along with the relevant inserter/extractor set.
That is, for the integer load/stores, there is only a single valid
indexing offset quantity and offset mode is allowed - The value is
always equivalent to the amount of data read/stored by the
operation and the offset is post-indexed for Load-Acquire RCpc, and
pre-indexed with writeback for Store-Release insns.
This indexing quantity/mode pair is selected by the setting of a
single bit in the instruction. To represent these insns, we add the
following operand types:
- AARCH64_OPND_RCPC3_ADDR_OPT_POSTIND
- AARCH64_OPND_RCPC3_ADDR_OPT_PREIND_WB
In the case of loads and stores involving SIMD/FP registers, the
optional offset is encoded as an 8-bit signed immediate, but neither
post-indexing or pre-indexing with writeback is available. This
created the need for an operand type similar to
AARCH64_OPND_ADDR_OFFSET, with the difference that FLD_index should
not be checked.
We thus introduce the AARCH64_OPND_RCPC3_ADDR_OFFSET operand, a
variant of AARCH64_OPND_ADDR_OFFSET, w/o the FLD_index bitfield.
Diffstat (limited to 'opcodes/aarch64-tbl.h')
| -rw-r--r-- | opcodes/aarch64-tbl.h | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 149265a..1092d63 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -7025,4 +7025,18 @@ const struct aarch64_opcode aarch64_opcode_table[] = "a list of 3 SVE vector registers") \ X(SVE_REGLIST, ins_sve_reglist, ext_sve_reglist_zt, "SME_Zt4", \ 4 << OPD_F_OD_LSB, F(FLD_SVE_Zt), \ - "a list of 4 SVE vector registers") + "a list of 4 SVE vector registers") \ + X(ADDRESS, ins_rcpc3_addr_opt_offset, ext_rcpc3_addr_opt_offset, \ + "RCPC3_ADDR_OPT_POSTIND", 0, F(FLD_opc2), \ + "an address with post-incrementing by ammount of loaded bytes") \ + X(ADDRESS, ins_rcpc3_addr_opt_offset, ext_rcpc3_addr_opt_offset, \ + "RCPC3_ADDR_OPT_PREIND_WB", 0, F(FLD_opc2), \ + "an address with pre-incrementing with write-back by ammount of stored bytes") \ + X(ADDRESS, ins_rcpc3_addr_opt_offset, ext_rcpc3_addr_opt_offset, \ + "RCPC3_ADDR_POSTIND", 0, F(), \ + "an address with post-incrementing by ammount of loaded bytes") \ + X(ADDRESS, ins_rcpc3_addr_opt_offset, ext_rcpc3_addr_opt_offset, \ + "RCPC3_ADDR_PREIND_WB", 0, F(), \ + "an address with pre-incrementing with write-back by ammount of stored bytes") \ + Y(ADDRESS, rcpc3_addr_offset, "RCPC3_ADDR_OFFSET", 0, F(FLD_Rn,FLD_imm9), \ + "an address with an optional 8-bit signed immediate offset") |