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| author | Srinath Parvathaneni <srinath.parvathaneni@arm.com> | 2024-01-15 09:37:32 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2024-01-15 11:45:41 +0000 |
| commit | 39092c7a1fb0927fbbdb40e1142de816d6f3f097 (patch) | |
| tree | 39c066e97256ea52262332db3601294caf5708b6 /opcodes/aarch64-tbl.h | |
| parent | 88601c2d941b004b443dc4bfdf3b93ea1983d136 (diff) | |
| download | fsf-binutils-gdb-39092c7a1fb0927fbbdb40e1142de816d6f3f097.zip fsf-binutils-gdb-39092c7a1fb0927fbbdb40e1142de816d6f3f097.tar.gz fsf-binutils-gdb-39092c7a1fb0927fbbdb40e1142de816d6f3f097.tar.bz2 | |
aarch64: Add SVE2.1 dupq, eorqv and extq instructions.
Hi,
This patch add support for SVE2.1 instruction dupq, eorqv and extq.
Regression testing for aarch64-none-elf target and found no regressions.
Ok for binutils-master?
Regards,
Srinath.
Diffstat (limited to 'opcodes/aarch64-tbl.h')
| -rw-r--r-- | opcodes/aarch64-tbl.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index f433257..07f4eb3 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -6337,6 +6337,10 @@ const struct aarch64_opcode aarch64_opcode_table[] = SVE2p1_INSNC("sminqv",0x040e2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0), SVE2p1_INSNC("umaxqv",0x040d2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0), SVE2p1_INSNC("uminqv",0x040f2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0), + SVE2p1_INSNC("eorqv",0x041d2000, 0xff3fe000, sve2_urqvs, 0, OP3 (Vd, SVE_Pg3, SVE_Zn), OP_SVE_vUS_BHSD_BHSD, F_OPD_SIZE, C_SCAN_MOVPRFX, 0), + + SVE2p1_INSN("dupq",0x05202400, 0xffe0fc00, sve_index1, 0, OP2 (SVE_Zd, SVE_Zn_5_INDEX), OP_SVE_VV_BHSD, 0, 0), + SVE2p1_INSN("extq",0x05602400, 0xfff0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zd, SVE_Zm_imm4), OP_SVE_BBB, 0, 0), {0, 0, 0, 0, 0, 0, {}, {}, 0, 0, 0, NULL}, }; @@ -6816,11 +6820,17 @@ const struct aarch64_opcode aarch64_opcode_table[] = Y(SVE_REG, sve_quad_index, "SVE_Zm4_11_INDEX", \ 4 << OPD_F_OD_LSB, F(FLD_SVE_i2h, FLD_SVE_i3l, FLD_SVE_imm4), \ "an indexed SVE vector register") \ + Y(SVE_REG, sve_quad_index, "SVE_Zm_imm4", \ + 5 << OPD_F_OD_LSB, F(FLD_SVE_Zm_5, FLD_SVE_imm4), \ + "an 4bit indexed SVE vector register") \ Y(SVE_REG, sve_quad_index, "SVE_Zm4_INDEX", \ 4 << OPD_F_OD_LSB, F(FLD_SVE_Zm_16), \ "an indexed SVE vector register") \ Y(SVE_REG, regno, "SVE_Zn", 0, F(FLD_SVE_Zn), \ "an SVE vector register") \ + Y(SVE_REG, sve_index_imm, "SVE_Zn_5_INDEX", 0, \ + F(FLD_SVE_Zn, FLD_SVE_i2h, FLD_SVE_tsz), \ + "a 5 bit idexed SVE vector register") \ Y(SVE_REG, sve_index, "SVE_Zn_INDEX", 0, F(FLD_SVE_Zn), \ "an indexed SVE vector register") \ Y(SVE_REGLIST, sve_reglist, "SVE_ZnxN", 0, F(FLD_SVE_Zn), \ |