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| author | Alex Coplan <alex.coplan@arm.com> | 2020-04-30 15:47:30 +0100 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2020-04-30 15:47:30 +0100 |
| commit | 09c1e68a162f9a2c2cadee916387a147a8af44b7 (patch) | |
| tree | a0c677f1aa242b8e99f55a6c9856e24043e8de23 /opcodes/aarch64-tbl.h | |
| parent | 8a8a1171237d45e20b2ebb18ee2d3f8686e01b82 (diff) | |
| download | fsf-binutils-gdb-09c1e68a162f9a2c2cadee916387a147a8af44b7.zip fsf-binutils-gdb-09c1e68a162f9a2c2cadee916387a147a8af44b7.tar.gz fsf-binutils-gdb-09c1e68a162f9a2c2cadee916387a147a8af44b7.tar.bz2 | |
AArch64: add GAS support for UDF instruction
binutils * testsuite/binutils-all/aarch64/in-order-all.d: Update to use new
disassembly.
* testsuite/binutils-all/aarch64/out-of-order-all.d: Likewise.
ld/ * testsuite/ld-aarch64/erratum843419_tls_ie.d: Use udf in disassembly.
* testsuite/ld-aarch64/farcall-b-section.d: Likewise.
* testsuite/ld-aarch64/farcall-back.d: Likewise.
* testsuite/ld-aarch64/farcall-bl-section.d: Likewise.
gas/ * config/tc-aarch64.c (fix_insn): Implement for AARCH64_OPND_UNDEFINED.
(parse_operands): Implement for AARCH64_OPND_UNDEFINED.
* testsuite/gas/aarch64/udf.s: New.
* testsuite/gas/aarch64/udf.d: New.
* testsuite/gas/aarch64/udf-invalid.s: New.
* testsuite/gas/aarch64/udf-invalid.l: New.
* testsuite/gas/aarch64/udf-invalid.d: New.
include * opcode/aarch64.h (enum aarch64_opnd): Add AARCH64_OPND_UNDEFINED.
opcodes * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
* aarch64-opc.c (fields): Add entry for FLD_imm16_2.
(operand_general_constraint_met_p): validate AARCH64_OPND_UNDEFINED.
* aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry for
FLD_imm16_2.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
Diffstat (limited to 'opcodes/aarch64-tbl.h')
| -rw-r--r-- | opcodes/aarch64-tbl.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 46c0386..5ad7180 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -3354,6 +3354,7 @@ struct aarch64_opcode aarch64_opcode_table[] = CORE_INSN ("smc", 0xd4000003, 0xffe0001f, exception, 0, OP1 (EXCEPTION), {}, 0), CORE_INSN ("brk", 0xd4200000, 0xffe0001f, exception, 0, OP1 (EXCEPTION), {}, 0), CORE_INSN ("hlt", 0xd4400000, 0xffe0001f, exception, 0, OP1 (EXCEPTION), {}, 0), + CORE_INSN ("udf", 0x00000000, 0xffff0000, exception, 0, OP1 (UNDEFINED), {}, 0), CORE_INSN ("dcps1", 0xd4a00001, 0xffe0001f, exception, 0, OP1 (EXCEPTION), {}, F_OPD0_OPT | F_DEFAULT (0)), CORE_INSN ("dcps2", 0xd4a00002, 0xffe0001f, exception, 0, OP1 (EXCEPTION), {}, F_OPD0_OPT | F_DEFAULT (0)), CORE_INSN ("dcps3", 0xd4a00003, 0xffe0001f, exception, 0, OP1 (EXCEPTION), {}, F_OPD0_OPT | F_DEFAULT (0)), @@ -5238,6 +5239,8 @@ struct aarch64_opcode aarch64_opcode_table[] = "the bit number to be tested") \ Y(IMMEDIATE, imm, "EXCEPTION", 0, F(FLD_imm16), \ "a 16-bit unsigned immediate") \ + Y(IMMEDIATE, imm, "UNDEFINED", 0, F(FLD_imm16_2), \ + "a 16-bit unsigned immediate") \ Y(IMMEDIATE, imm, "CCMP_IMM", 0, F(FLD_imm5), \ "a 5-bit unsigned immediate") \ Y(IMMEDIATE, imm, "SIMM5", OPD_F_SEXT, F(FLD_imm5), \ |