diff options
| author | Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> | 2020-10-28 14:16:39 +0000 |
|---|---|---|
| committer | Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> | 2020-10-28 14:19:42 +0000 |
| commit | dd4a72c859a6896d6df824535590ccbb3631fdd7 (patch) | |
| tree | 7999561fc2abf2203654a950546803413b3930b8 /opcodes/aarch64-tbl.h | |
| parent | 82503ca7ed8301dc076919d5010bf981e35b1314 (diff) | |
| download | fsf-binutils-gdb-dd4a72c859a6896d6df824535590ccbb3631fdd7.zip fsf-binutils-gdb-dd4a72c859a6896d6df824535590ccbb3631fdd7.tar.gz fsf-binutils-gdb-dd4a72c859a6896d6df824535590ccbb3631fdd7.tar.bz2 | |
aarch64: Add CSR PDEC instruction
This patch adds:
+ New feature +csre to -march command line.
+ New instruction CSR PDEC associated with CSRE feature.
Please note that CSRE system registers were already upstreamed. This patch
should finalize CSRE feature implementation.
CSRE feature adds CSR PDEC (Decrements Call stack pointer by the size of
a Call stack record) instruction. Although this instruction has operand
(PDEC) it's instruction's only operand. PDEC forces instruction field Rt
to be set to 0b1111. This results in fixed opcode of the instruction.
gas/ChangeLog:
2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* NEWS: Update docs.
* config/tc-aarch64.c (parse_csr_operand): New operand parser.
(parse_operands): Call to CSR operand parser.
* testsuite/gas/aarch64/csre_csr-invalid.d: New test.
* testsuite/gas/aarch64/csre_csr-invalid.l: New test.
* testsuite/gas/aarch64/csre_csr-invalid.s: New test.
* testsuite/gas/aarch64/csre_csr.d: New test.
* testsuite/gas/aarch64/csre_csr.s: New test.
include/ChangeLog:
2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_CSRE): New -march feature.
(enum aarch64_opnd): New CSR instruction field AARCH64_OPND_CSRE_CSR.
opcodes/ChangeLog:
2020-10-27 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
* aarch64-opc.c (aarch64_print_operand): CSR PDEC operand print-out.
* aarch64-tbl.h (CSRE): New CSRE feature handler.
(_CSRE_INSN): New CSRE instruction type.
(struct aarch64_opcode): New 'csre' entry for a CSRE CLI feature.
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Regenerated.
* aarch64-opc-2.c: Regenerated.
Diffstat (limited to 'opcodes/aarch64-tbl.h')
| -rw-r--r-- | opcodes/aarch64-tbl.h | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index a3014c1..3ec18ca 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -2410,6 +2410,8 @@ static const aarch64_feature_set aarch64_feature_f64mm_sve = | AARCH64_FEATURE_SVE, 0); static const aarch64_feature_set aarch64_feature_v8_r = AARCH64_FEATURE (AARCH64_FEATURE_V8_R, 0); +static const aarch64_feature_set aarch64_feature_csre = + AARCH64_FEATURE (AARCH64_FEATURE_CSRE, 0); #define CORE &aarch64_feature_v8 @@ -2456,6 +2458,7 @@ static const aarch64_feature_set aarch64_feature_v8_r = #define I8MM &aarch64_feature_i8mm #define ARMV8_R &aarch64_feature_v8_r #define ARMV8_7 &aarch64_feature_v8_7 +#define CSRE &aarch64_feature_csre #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL } @@ -2563,6 +2566,9 @@ static const aarch64_feature_set aarch64_feature_v8_r = { NAME, OPCODE, MASK, CLASS, 0, ARMV8_R, OPS, QUALS, FLAGS, 0, 0, NULL } #define V8_7_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, ARMV8_7, OPS, QUALS, FLAGS, 0, 0, NULL } +#define _CSRE_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ + { NAME, OPCODE, MASK, CLASS, 0, CSRE, OPS, QUALS, FLAGS, 0, 0, NULL } + struct aarch64_opcode aarch64_opcode_table[] = { @@ -3833,6 +3839,8 @@ struct aarch64_opcode aarch64_opcode_table[] = _TME_INSN ("tcommit", 0xd503307f, 0xffffffff, 0, 0, OP0 (), {}, 0), _TME_INSN ("ttest", 0xd5233160, 0xffffffe0, 0, 0, OP1 (Rd), QL_I1X, 0), _TME_INSN ("tcancel", 0xd4600000, 0xffe0001f, 0, 0, OP1 (TME_UIMM16), QL_IMM_NIL, 0), + /* CSRE Instructions. */ + _CSRE_INSN ("csr", 0xd50b721f, 0xffffffff, 0, OP1 (CSRE_CSR), {}, 0), /* System. */ CORE_INSN ("msr", 0xd500401f, 0xfff8f01f, ic_system, 0, OP2 (PSTATEFIELD, UIMM4), {}, F_SYS_WRITE), CORE_INSN ("hint",0xd503201f, 0xfffff01f, ic_system, 0, OP1 (UIMM7), {}, F_HAS_ALIAS), |