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| author | Sudi Das <sudi.das@arm.com> | 2019-01-25 14:15:45 +0000 |
|---|---|---|
| committer | Tamar Christina <tamar.christina@arm.com> | 2019-01-25 14:49:52 +0000 |
| commit | 20a4ca5524b9bde2f5dfb19661570c25a3b05e5d (patch) | |
| tree | e7db661e08015c096cf021dd685d33a56e9d9d1b /opcodes/aarch64-tbl.h | |
| parent | 550fd7bf6858cd708c54ec90412ffb653a932c3d (diff) | |
| download | fsf-binutils-gdb-20a4ca5524b9bde2f5dfb19661570c25a3b05e5d.zip fsf-binutils-gdb-20a4ca5524b9bde2f5dfb19661570c25a3b05e5d.tar.gz fsf-binutils-gdb-20a4ca5524b9bde2f5dfb19661570c25a3b05e5d.tar.bz2 | |
AArch64: Add new STZGM instruction for Armv8.5-A Memory Tagging Extension.
This patch is part of a series of patches to introduce a few changes to the
Armv8.5-A Memory Tagging Extension. This patch adds the new STZGM instruction.
STGZM Xt, [<Xn|SP>]
Committed on behalf of Sudakshina Das.
*** gas/ChangeLog ***
* testsuite/gas/aarch64/armv8_5-a-memtag.d: New tests for stzgm.
* testsuite/gas/aarch64/armv8_5-a-memtag.s: Likewise.
* testsuite/gas/aarch64/illegal-memtag.l: Likewise.
* testsuite/gas/aarch64/illegal-memtag.s: Likewise.
*** opcodes/ChangeLog ***
* aarch64-asm-2.c: Regenerated.
* aarch64-dis-2.c: Likewise.
* aarch64-opc-2.c: Likewise.
* aarch64-tbl.h (aarch64_opcode): Add new stzgm.
Diffstat (limited to 'opcodes/aarch64-tbl.h')
| -rw-r--r-- | opcodes/aarch64-tbl.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index d4ecd6d..277293b 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -3324,6 +3324,7 @@ struct aarch64_opcode aarch64_opcode_table[] = RCPC_INSN ("ldaprb", 0x38bfc000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), RCPC_INSN ("ldaprh", 0x78bfc000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), RCPC_INSN ("ldapr", 0xb8bfc000, 0xbffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q), + MEMTAG_INSN ("stzgm", 0xd9200000, 0xfffffc00, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_X1NIL, 0), /* Limited Ordering Regions load/store instructions. */ _LOR_INSN ("ldlar", 0x88df7c00, 0xbfe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL, F_GPRSIZE_IN_Q), _LOR_INSN ("ldlarb", 0x08df7c00, 0xffe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0), |