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| author | James Greenhalgh <james.greenhalgh@arm.com> | 2018-01-09 11:28:04 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2018-01-09 11:28:04 +0000 |
| commit | be2e7d95414eb78f29312f30e62d4cabd55f9fda (patch) | |
| tree | 6c658b79344e6c086c93fe4b0a57e1ce9c37b7e9 /opcodes/aarch64-tbl.h | |
| parent | b1dc1806fad00fc5b2589164e964646c02a700fa (diff) | |
| download | fsf-binutils-gdb-be2e7d95414eb78f29312f30e62d4cabd55f9fda.zip fsf-binutils-gdb-be2e7d95414eb78f29312f30e62d4cabd55f9fda.tar.gz fsf-binutils-gdb-be2e7d95414eb78f29312f30e62d4cabd55f9fda.tar.bz2 | |
Add support for the AArch64's CSDB instruction.
CSDB is a new instruction which Arm has defined. It has the same encoding as
HINT #0x14 and is available at all architecture levels.
opcodes * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
gas * testsuite/gas/aarch64/system.d: Update expected results to expect
CSDB.
Diffstat (limited to 'opcodes/aarch64-tbl.h')
| -rw-r--r-- | opcodes/aarch64-tbl.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index f758eeb..12b980e 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -3455,6 +3455,7 @@ struct aarch64_opcode aarch64_opcode_table[] = CORE_INSN ("msr", 0xd500401f, 0xfff8f01f, ic_system, 0, OP2 (PSTATEFIELD, UIMM4), {}, 0), CORE_INSN ("hint",0xd503201f, 0xfffff01f, ic_system, 0, OP1 (UIMM7), {}, F_HAS_ALIAS), CORE_INSN ("nop", 0xd503201f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), + CORE_INSN ("csdb",0xd503229f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), CORE_INSN ("yield", 0xd503203f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), CORE_INSN ("wfe", 0xd503205f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), CORE_INSN ("wfi", 0xd503207f, 0xffffffff, ic_system, 0, OP0 (), {}, F_ALIAS), |