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| author | Sudakshina Das <sudi.das@arm.com> | 2018-09-26 10:52:51 +0100 |
|---|---|---|
| committer | Richard Earnshaw <Richard.Earnshaw@arm.com> | 2018-10-09 15:17:10 +0100 |
| commit | 2ac435d46608be7ef90f80aaf9ff48443aea571e (patch) | |
| tree | 9adf96d34751880e859e59074696a51b5b8debc4 /opcodes/aarch64-tbl.h | |
| parent | 68dfbb92ef5f013a315d652c88ede2082c16a88e (diff) | |
| download | fsf-binutils-gdb-2ac435d46608be7ef90f80aaf9ff48443aea571e.zip fsf-binutils-gdb-2ac435d46608be7ef90f80aaf9ff48443aea571e.tar.gz fsf-binutils-gdb-2ac435d46608be7ef90f80aaf9ff48443aea571e.tar.bz2 | |
[PATCH, BINUTILS, AARCH64, 4/9] Add Execution and Data Restriction instructions
This patch is part of the patch series to add support for ARMv8.5-A
extensions.
(https://developer.arm.com/products/architecture/cpu-architecture/a-profile/docs/ddi0596/a/a64-base-instructions-alphabetic-order)
This patch adds the prediction restriction instructions (that is, cfp,
dvp, cpp). These instructions are retrospectively made optional for
all versions of the architecture from ARMv8.0 to ARMv8.4 and is
mandatory from ARMv8.5. Hence adding a new +predres which can be used
by the older architectures.
*** include/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* opcode/aarch64.h (AARCH64_FEATURE_PREDRES): New.
(AARCH64_ARCH_V8_5): Add AARCH64_FEATURE_PREDRES by default.
(aarch64_opnd): Add AARCH64_OPND_SYSREG_SR.
(aarch64_sys_regs_sr): Declare new table.
*** opcodes/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* aarch64-dis.c (aarch64_ext_sysins_op): Add case for
AARCH64_OPND_SYSREG_SR.
* aarch64-opc.c (aarch64_print_operand): Likewise.
(aarch64_sys_regs_sr): Define table.
(aarch64_sys_ins_reg_supported_p): Check for RCTX with
AARCH64_FEATURE_PREDRES.
* aarch64-tbl.h (aarch64_feature_predres): New.
(PREDRES, PREDRES_INSN): New.
(aarch64_opcode_table): Add entries for cfp, dvp and cpp.
(AARCH64_OPERANDS): Add new description for SYSREG_SR.
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
*** gas/ChangeLog ***
2018-10-09 Sudakshina Das <sudi.das@arm.com>
* config/tc-aarch64.c (aarch64_sys_regs_sr_hsh): New.
(parse_operands): Add entry for AARCH64_OPND_SYSREG_SR.
(md_begin): Allocate and initialize aarch64_sys_regs_sr_hsh
with aarch64_sys_regs_sr.
(aarch64_features): Add new "predres" option for older
architectures.
* doc/c-aarch64.texi: Document the same.
* testsuite/gas/aarch64/sysreg-4.s: New.
* testsuite/gas/aarch64/sysreg-4.d: New.
* testsuite/gas/aarch64/illegal-sysreg-4.d: New.
* testsuite/gas/aarch64/illegal-sysreg-4.l: New.
* testsuite/gas/aarch64/predres.s: New.
* testsuite/gas/aarch64/predres.d: New.
Diffstat (limited to 'opcodes/aarch64-tbl.h')
| -rw-r--r-- | opcodes/aarch64-tbl.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index ce85bce..6318ba9 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -2167,6 +2167,8 @@ static const aarch64_feature_set aarch64_feature_frintts = AARCH64_FEATURE (AARCH64_FEATURE_FRINTTS, 0); static const aarch64_feature_set aarch64_feature_sb = AARCH64_FEATURE (AARCH64_FEATURE_SB, 0); +static const aarch64_feature_set aarch64_feature_predres = + AARCH64_FEATURE (AARCH64_FEATURE_PREDRES, 0); #define CORE &aarch64_feature_v8 @@ -2199,6 +2201,7 @@ static const aarch64_feature_set aarch64_feature_sb = #define FLAGMANIP &aarch64_feature_flagmanip #define FRINTTS &aarch64_feature_frintts #define SB &aarch64_feature_sb +#define PREDRES &aarch64_feature_predres #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL } @@ -2258,6 +2261,8 @@ static const aarch64_feature_set aarch64_feature_sb = { NAME, OPCODE, MASK, CLASS, 0, FRINTTS, OPS, QUALS, FLAGS, 0, 0, NULL } #define SB_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, 0, SB, OPS, QUALS, FLAGS, 0, 0, NULL } +#define PREDRES_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \ + { NAME, OPCODE, MASK, CLASS, 0, PREDRES, OPS, QUALS, FLAGS, 0, 0, NULL } struct aarch64_opcode aarch64_opcode_table[] = { @@ -3529,6 +3534,9 @@ struct aarch64_opcode aarch64_opcode_table[] = CORE_INSN ("dc", 0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_DC, Rt), QL_SRC_X, F_ALIAS), CORE_INSN ("ic", 0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_IC, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)), CORE_INSN ("tlbi",0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_TLBI, Rt_SYS), QL_SRC_X, F_ALIAS | F_OPD1_OPT | F_DEFAULT (0x1F)), + PREDRES_INSN ("cfp", 0xd50b7380, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS), + PREDRES_INSN ("dvp", 0xd50b73a0, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS), + PREDRES_INSN ("cpp", 0xd50b73e0, 0xffffffe0, ic_system, OP2 (SYSREG_SR, Rt), QL_SRC_X, F_ALIAS), CORE_INSN ("msr", 0xd5000000, 0xffe00000, ic_system, 0, OP2 (SYSREG, Rt), QL_SRC_X, F_SYS_WRITE), CORE_INSN ("sysl",0xd5280000, 0xfff80000, ic_system, 0, OP5 (Rt, UIMM3_OP1, CRn, CRm, UIMM3_OP2), QL_SYSL, 0), CORE_INSN ("mrs", 0xd5200000, 0xffe00000, ic_system, 0, OP2 (Rt, SYSREG), QL_DST_X, F_SYS_READ), @@ -4611,6 +4619,8 @@ struct aarch64_opcode aarch64_opcode_table[] = "an instruction cache maintenance operation specifier") \ Y(SYSTEM, sysins_op, "SYSREG_TLBI", 0, F(), \ "a TBL invalidation operation specifier") \ + Y(SYSTEM, sysins_op, "SYSREG_SR", 0, F(), \ + "a Speculation Restriction option name (RCTX)") \ Y(SYSTEM, barrier, "BARRIER", 0, F(), \ "a barrier option name") \ Y(SYSTEM, barrier, "BARRIER_ISB", 0, F(), \ |