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| author | Richard Sandiford <richard.sandiford@arm.com> | 2019-07-02 10:51:05 +0100 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2019-07-02 10:51:05 +0100 |
| commit | 8941884429c305ad42a41f759a98c8cca4d4aacc (patch) | |
| tree | c198a6e2bbe1d26851bc4716b68840793ef5359c /opcodes/aarch64-opc.c | |
| parent | 390b205f456be85e309570f1b6e9b75f27194de7 (diff) | |
| download | fsf-binutils-gdb-8941884429c305ad42a41f759a98c8cca4d4aacc.zip fsf-binutils-gdb-8941884429c305ad42a41f759a98c8cca4d4aacc.tar.gz fsf-binutils-gdb-8941884429c305ad42a41f759a98c8cca4d4aacc.tar.bz2 | |
[AArch64] Fix bogus MOVPRFX warning for GPR form of CPY
One of the MOVPRFX tests has:
output register of preceding `movprfx' used as input at operand 3 -- `cpy z1.d,p1/m,x1'
But X1 and Z1 are not the same register, so the instruction is
actually OK.
2019-07-02 Richard Sandiford <richard.sandiford@arm.com>
opcodes/
* aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
registers in an instruction prefixed by MOVPRFX.
gas/
* testsuite/gas/aarch64/sve-movprfx_25.s: Allow CPY Z1.D.P1/M,X1
to be prefixed by MOVPRFX.
* testsuite/gas/aarch64/sve-movprfx_25.d: Update accordingly.
* testsuite/gas/aarch64/sve-movprfx_25.l: Likewise.
Diffstat (limited to 'opcodes/aarch64-opc.c')
| -rw-r--r-- | opcodes/aarch64-opc.c | 5 |
1 files changed, 0 insertions, 5 deletions
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 00ff94d..7ffec2d 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -4968,11 +4968,6 @@ verify_constraints (const struct aarch64_inst *inst, case AARCH64_OPND_Vm: case AARCH64_OPND_Sn: case AARCH64_OPND_Sm: - case AARCH64_OPND_Rn: - case AARCH64_OPND_Rm: - case AARCH64_OPND_Rn_SP: - case AARCH64_OPND_Rt_SP: - case AARCH64_OPND_Rm_SP: if (inst_op.reg.regno == blk_dest.reg.regno) { num_op_used++; |