[AArch64][SVE 21/32] Add Zn and Pn registers

This patch adds the Zn and Pn registers, and associated fields and
operands.

include/
	* opcode/aarch64.h (AARCH64_OPND_CLASS_SVE_REG): New
	aarch64_operand_class.
	(AARCH64_OPND_CLASS_PRED_REG): Likewise.
	(AARCH64_OPND_SVE_Pd, AARCH64_OPND_SVE_Pg3, AARCH64_OPND_SVE_Pg4_5)
	(AARCH64_OPND_SVE_Pg4_10, AARCH64_OPND_SVE_Pg4_16)
	(AARCH64_OPND_SVE_Pm, AARCH64_OPND_SVE_Pn, AARCH64_OPND_SVE_Pt)
	(AARCH64_OPND_SVE_Za_5, AARCH64_OPND_SVE_Za_16, AARCH64_OPND_SVE_Zd)
	(AARCH64_OPND_SVE_Zm_5, AARCH64_OPND_SVE_Zm_16, AARCH64_OPND_SVE_Zn)
	(AARCH64_OPND_SVE_Zn_INDEX, AARCH64_OPND_SVE_ZnxN)
	(AARCH64_OPND_SVE_Zt, AARCH64_OPND_SVE_ZtxN): New aarch64_opnds.

opcodes/
	* aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
	* aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
	(FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
	(FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
	(FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
	* aarch64-opc.c (fields): Add corresponding entries here.
	(operand_general_constraint_met_p): Check that SVE register lists
	have the correct length.  Check the ranges of SVE index registers.
	Check for cases where p8-p15 are used in 3-bit predicate fields.
	(aarch64_print_operand): Handle the new SVE operands.
	* aarch64-opc-2.c: Regenerate.
	* aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
	* aarch64-asm.c (aarch64_ins_sve_index): New function.
	(aarch64_ins_sve_reglist): Likewise.
	* aarch64-asm-2.c: Regenerate.
	* aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
	* aarch64-dis.c (aarch64_ext_sve_index): New function.
	(aarch64_ext_sve_reglist): Likewise.
	* aarch64-dis-2.c: Regenerate.

gas/
	* config/tc-aarch64.c (NTA_HASVARWIDTH): New macro.
	(AARCH64_REG_TYPES): Add ZN and PN.
	(get_reg_expected_msg): Handle them.
	(parse_vector_type_for_operand): Add a reg_type parameter.
	Skip the width for Zn and Pn registers.
	(parse_typed_reg): Extend vector handling to Zn and Pn.  Update the
	call to parse_vector_type_for_operand.  Set HASVARTYPE for Zn and Pn,
	expecting the width to be 0.
	(parse_vector_reg_list): Restrict error about [BHSD]nn operands to
	REG_TYPE_VN.
	(vectype_to_qualifier): Use S_[BHSD] qualifiers for NTA_HASVARWIDTH.
	(parse_operands): Handle the new Zn and Pn operands.
	(REGSET16): New macro, split out from...
	(REGSET31): ...here.
	(reg_names): Add Zn and Pn entries.

1 files changed, 34 insertions, 0 deletions

diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index 4c3b521..ab93234 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -1185,6 +1185,40 @@ aarch64_ext_reg_shifted (const aarch64_operand *self ATTRIBUTE_UNUSED,
 
   return 1;
 }
+
+/* Decode Zn[MM], where MM has a 7-bit triangular encoding.  The fields
+   array specifies which field to use for Zn.  MM is encoded in the
+   concatenation of imm5 and SVE_tszh, with imm5 being the less
+   significant part.  */
+int
+aarch64_ext_sve_index (const aarch64_operand *self,
+		       aarch64_opnd_info *info, aarch64_insn code,
+		       const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+  int val;
+
+  info->reglane.regno = extract_field (self->fields[0], code, 0);
+  val = extract_fields (code, 0, 2, FLD_SVE_tszh, FLD_imm5);
+  if ((val & 15) == 0)
+    return 0;
+  while ((val & 1) == 0)
+    val /= 2;
+  info->reglane.index = val / 2;
+  return 1;
+}
+
+/* Decode {Zn.<T> - Zm.<T>}.  The fields array specifies which field
+   to use for Zn.  The opcode-dependent value specifies the number
+   of registers in the list.  */
+int
+aarch64_ext_sve_reglist (const aarch64_operand *self,
+			 aarch64_opnd_info *info, aarch64_insn code,
+			 const aarch64_inst *inst ATTRIBUTE_UNUSED)
+{
+  info->reglist.first_regno = extract_field (self->fields[0], code, 0);
+  info->reglist.num_regs = get_opcode_dependent_value (inst->opcode);
+  return 1;
+}
 
 /* Bitfields that are commonly used to encode certain operands' information
    may be partially used as part of the base opcode in some instructions.