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author | Matthew Wahab <matthew.wahab@arm.com> | 2015-11-27 15:25:08 +0000 |
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committer | Matthew Wahab <matthew.wahab@arm.com> | 2015-11-27 15:28:42 +0000 |
commit | d685192a58d4c198633bd0e69cfe0a114576e98a (patch) | |
tree | 8b57e30467eb5a4d74ddf557c3822dd8f1016070 /opcodes/aarch64-asm.c | |
parent | e19616610d7327664f99215a69cb326682742dc3 (diff) | |
download | fsf-binutils-gdb-d685192a58d4c198633bd0e69cfe0a114576e98a.zip fsf-binutils-gdb-d685192a58d4c198633bd0e69cfe0a114576e98a.tar.gz fsf-binutils-gdb-d685192a58d4c198633bd0e69cfe0a114576e98a.tar.bz2 |
[AArch64] Add ARMv8.2 instructions BFC and REV64.
ARMv8.2 adds two new instructions: BFC as an alias for BFM and REV64 as
an alias for REV. This patch set adds support for these to binutils,
enabled when the -march=armv8.2-a is given. It depends on the support
for an instruction being its preferred form which was added in an
earlier patch.
This patch adds the alias BFC <Rd>, #<imm>, #<width> as the preferred
form for BFM when the source is a zero register and the conditions for
using the BFI form are met (in other words, BFC is the preferred form
for BFI <Rd>, <Rs>, #<imm>, #<width> when the <Rs> is a zero register).
gas/testsuite/
2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
* gas/aarch64/alias-2.d: New.
* gas/aarch64/alias-2.s: New.
include/opcode/
2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
* aarch64.h (aarch64_op): Add OP_BFC.
opcodes/
2015-11-27 Matthew Wahab <matthew.wahab@arm.com>
* aarch64-asm-2.c: Regenerate.
* aarch64-asm.c (convert_bfc_to_bfm): New.
(convert_to_real): Add case for OP_BFC.
* aarch64-dis-2.c: Regenerate.
* aarch64-dis.c: (convert_bfm_to_bfc): New.
(convert_to_alias): Add case for OP_BFC.
* aarch64-opc-2.c: Regenerate.
* aarch64-opc.c (operand_general_constraint_met_p): Weaken assert
to allow width operand in three-operand instructions.
* aarch64-tbl.h (QL_BF1): New.
(aarch64_feature_v8_2): New.
(ARMV8_2): New.
(aarch64_opcode_table): Add "bfc".
Change-Id: I6efe318b2538ba11f0caece7c6d70957441c872b
Diffstat (limited to 'opcodes/aarch64-asm.c')
-rw-r--r-- | opcodes/aarch64-asm.c | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c index 9689440..ef64501 100644 --- a/opcodes/aarch64-asm.c +++ b/opcodes/aarch64-asm.c @@ -1039,6 +1039,37 @@ convert_bfi_to_bfm (aarch64_inst *inst) } /* The instruction written: + BFC <Xd>, #<lsb>, #<width> + is equivalent to: + BFM <Xd>, XZR, #((64-<lsb>)&0x3f), #(<width>-1). */ + +static void +convert_bfc_to_bfm (aarch64_inst *inst) +{ + int64_t lsb, width; + + /* Insert XZR. */ + copy_operand_info (inst, 3, 2); + copy_operand_info (inst, 2, 1); + copy_operand_info (inst, 2, 0); + inst->operands[1].reg.regno = 0x1f; + + /* Convert the immedate operand. */ + lsb = inst->operands[2].imm.value; + width = inst->operands[3].imm.value; + if (inst->operands[2].qualifier == AARCH64_OPND_QLF_imm_0_31) + { + inst->operands[2].imm.value = (32 - lsb) & 0x1f; + inst->operands[3].imm.value = width - 1; + } + else + { + inst->operands[2].imm.value = (64 - lsb) & 0x3f; + inst->operands[3].imm.value = width - 1; + } +} + +/* The instruction written: LSL <Xd>, <Xn>, #<shift> is equivalent to: UBFM <Xd>, <Xn>, #((64-<shift>)&0x3f), #(63-<shift>). */ @@ -1171,6 +1202,9 @@ convert_to_real (aarch64_inst *inst, const aarch64_opcode *real) case OP_UBFIZ: convert_bfi_to_bfm (inst); break; + case OP_BFC: + convert_bfc_to_bfm (inst); + break; case OP_MOV_V: convert_mov_to_orr (inst); break; |