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author | Kuan-Lin Chen <kuanlinchentw@gmail.com> | 2014-09-10 09:46:32 +0800 |
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committer | Kuan-Lin Chen <kuanlinchentw@gmail.com> | 2014-09-16 12:28:11 +0800 |
commit | 40c7a7cb74ee4a9ec0830d734198fcd0e99c3a37 (patch) | |
tree | b28e7367173b15a3be3b1dd05dafa6e811f02f5a /opcodes/ChangeLog | |
parent | 5b636fed3a28c9237c187999490f8e58d54b2d83 (diff) | |
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NDS32/opcodes: Add audio ISA extension and modify the disassemble implemnt.
First, add nds32 audio ISA extension including opcodes and registers.
Second, redesign the disassemble implement.
The original disassemble decode instruction opcode using switch-case.
It is hard to synchronize when adding new instructions.
Therefore, the new implement reuses nds32_opcodes to dump the instructions.
Diffstat (limited to 'opcodes/ChangeLog')
-rw-r--r-- | opcodes/ChangeLog | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index ecab314..42e09dd 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,21 @@ +2014-09-16 Kuan-Lin Chen <kuanlinchentw@gmail.com> + + * nds32-asm.c (nds32_opcodes, operand_fields, keyword_im5_i, + keyword_im5_m, keyword_accumulator, keyword_aridx, keyword_aridx2, + keyword_aridxi): Add audio ISA extension. + (keyword_gpr, keyword_usr, keyword_sr, keyword_cp, keyword_cpr, + keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm, keyword_dpref_st, + keyword_cctl_lv, keyword_standby_st, keyword_msync_st): Adjust scrope + for nds32-dis.c using. + (build_opcode_syntax): Remove dead code. + (parse_re, parse_a30b20, parse_rt21, parse_rte_start, parse_rte_end, + parse_rte69_start, parse_rte69_end, parse_im5_ip, parse_im5_mr, + parse_im6_ip, parse_im6_iq, parse_im6_mr, parse_im6_ms): Add audio ISA + operand parser. + * nds32-asm.h: Declare. + * nds32-dis.c: Use array nds32_opcodes to disassemble instead of + decoding by switch. + 2014-09-15 Andrew Bennett <andrew.bennett@imgtec.com> Matthew Fortune <matthew.fortune@imgtec.com> |