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| author | Tsukasa OI <research_trasio@irq.a4lg.com> | 2022-05-27 20:25:53 +0900 |
|---|---|---|
| committer | Tsukasa OI <research_trasio@irq.a4lg.com> | 2022-09-30 15:10:27 +0000 |
| commit | 38cb335c7645d70eff612efd33ba5e52d9591802 (patch) | |
| tree | 6329f48d53a956e5566d979c7b312d2d11fa6ce1 /libdecnumber | |
| parent | a6eeb20a42a854f9127dcf1a0b54ed8c4f50f27c (diff) | |
| download | fsf-binutils-gdb-38cb335c7645d70eff612efd33ba5e52d9591802.zip fsf-binutils-gdb-38cb335c7645d70eff612efd33ba5e52d9591802.tar.gz fsf-binutils-gdb-38cb335c7645d70eff612efd33ba5e52d9591802.tar.bz2 | |
RISC-V: Reorganize and enhance 'Zfinx' tests
This commit adds certain test cases for 'Zfinx'/'Zdinx'/'Zqinx' extensions
and reorganizes them, fixing coding style while improving coverage.
This is partially based on jiawei's 'Zhinx' testcases.
gas/ChangeLog:
* testsuite/gas/riscv/zfinx.s: Use different registers for
better encode space testing. Make indentation consistent.
Add tests for instruction with rounding mode. Change march
to minimum required extensions. Remove source line.
* testsuite/gas/riscv/zfinx.d: Likewise.
* testsuite/gas/riscv/zdinx.s: Likewise.
* testsuite/gas/riscv/zdinx.d: Likewise.
* testsuite/gas/riscv/zqinx.s: Likewise.
Also use even-numbered registers to use valid register pairs.
* testsuite/gas/riscv/zqinx.d: Likewise.
Signed-off-by: Tsukasa OI <research_trasio@irq.a4lg.com>
Signed-off-by: jiawei <jiawei@iscas.ac.cn>
Diffstat (limited to 'libdecnumber')
0 files changed, 0 insertions, 0 deletions