RISC-V: Updated the default ISA spec to 20191213.

Update the default ISA spec from 2.2 to 20191213 will change the default
version of i from 2.0 to 2.1.  Since zicsr and zifencei are separated
from i 2.1, users need to add them in the architecture string if they need
fence.i and csr instructions.  Besides, we also allow old ISA spec can
recognize zicsr and zifencei, but we won't output them since they are
already included in the i extension when i's version is less than 2.1.

bfd/
	* elfxx-riscv.c (riscv_parse_add_subset): Allow old ISA spec can
	recognize zicsr and zifencei.
gas/
	* config/tc-riscv.c (DEFAULT_RISCV_ISA_SPEC): Updated to 20191213.
	* testsuite/gas/riscv/csr-version-1p10.d: Added zicsr to -march since
	the default version of i is 2.1.
	* testsuite/gas/riscv/csr-version-1p11.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p12.d: Likewise.
	* testsuite/gas/riscv/csr-version-1p9p1.d: Likewise.
	* testsuite/gas/riscv/option-arch-03.d: Updated i's version to 2.1.
	* testsuite/gas/riscv/option-arch-03.s: Likewise.
ld/
	* testsuite/ld-riscv-elf/call-relax.d: Added zicsr to -march since
	the default version of i is 2.1.
	* testsuite/ld-riscv-elf/attr-merge-arch-01.d: Updated i's version to 2.1.
	* testsuite/ld-riscv-elf/attr-merge-arch-01a.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-01b.: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-02.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-02a.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-02b.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-03.d: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-03a.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-03b.s: Likewise.
	* testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d: Added zifencei
	into Tag_RISCV_arch since it is added implied when i's version is
	larger than 2.1.

11 files changed, 11 insertions, 11 deletions

diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
index c148cdb..a4b0322 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01.d
@@ -6,4 +6,4 @@
 
 Attribute Section: riscv
 File Attributes
-  Tag_RISCV_arch: "rv32i2p0_m2p0"
+  Tag_RISCV_arch: "rv32i2p1_m2p0"
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01a.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01a.s
index acc98a5..ea097f9 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01a.s
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01a.s
@@ -1 +1 @@
-	.attribute arch, "rv32i2p0_m2p0"
+	.attribute arch, "rv32i2p1_m2p0"
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01b.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01b.s
index acc98a5..ea097f9 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-01b.s
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-01b.s
@@ -1 +1 @@
-	.attribute arch, "rv32i2p0_m2p0"
+	.attribute arch, "rv32i2p1_m2p0"
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
index bc0e0fd..852fd55 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02.d
@@ -6,4 +6,4 @@
 
 Attribute Section: riscv
 File Attributes
-  Tag_RISCV_arch: "rv32i2p0_m2p0"
+  Tag_RISCV_arch: "rv32i2p1_m2p0"
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02a.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02a.s
index acc98a5..ea097f9 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02a.s
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02a.s
@@ -1 +1 @@
-	.attribute arch, "rv32i2p0_m2p0"
+	.attribute arch, "rv32i2p1_m2p0"
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02b.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02b.s
index 65d0fef..610c7e5 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-02b.s
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-02b.s
@@ -1 +1 @@
-	.attribute arch, "rv32i2p0"
+	.attribute arch, "rv32i2p1"
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
index 374a043..c1cf808 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03.d
@@ -6,4 +6,4 @@
 
 Attribute Section: riscv
 File Attributes
-  Tag_RISCV_arch: "rv32i2p0_m2p0_xbar2p0_xfoo2p0"
+  Tag_RISCV_arch: "rv32i2p1_m2p0_xbar2p0_xfoo2p0"
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03a.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03a.s
index b86cc55..3a9fb97 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03a.s
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03a.s
@@ -1 +1 @@
-	.attribute arch, "rv32i2p0_m2p0_xfoo2p0"
+	.attribute arch, "rv32i2p1_m2p0_xfoo2p0"
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03b.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03b.s
index 376e373..878f2de 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-03b.s
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-03b.s
@@ -1 +1 @@
-	.attribute arch, "rv32i2p0_xbar2p0"
+	.attribute arch, "rv32i2p1_xbar2p0"
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d
index 3f4935d..2f2638a 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d
@@ -23,5 +23,5 @@
 
 Attribute Section: riscv
 File Attributes
-  Tag_RISCV_arch: "rv32i4p6_m4p7_a4p8_zicsr4p9_xunknown4p0"
+  Tag_RISCV_arch: "rv32i4p6_m4p7_a4p8_zicsr4p9_zifencei2p0_xunknown4p0"
 #..
diff --git a/ld/testsuite/ld-riscv-elf/call-relax.d b/ld/testsuite/ld-riscv-elf/call-relax.d
index c6022be..f8f0229 100644
--- a/ld/testsuite/ld-riscv-elf/call-relax.d
+++ b/ld/testsuite/ld-riscv-elf/call-relax.d
@@ -3,7 +3,7 @@
 #source: call-relax-1.s
 #source: call-relax-2.s
 #source: call-relax-3.s
-#as: -march=rv32ic -mno-arch-attr
+#as: -march=rv32ic_zicsr -mno-arch-attr
 #ld: -m[riscv_choose_ilp32_emul]
 #objdump: -d
 #pass