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authorNelson Chu <nelson.chu@sifive.com>2020-10-06 20:48:23 -0700
committerNelson Chu <nelson.chu@sifive.com>2020-10-16 10:11:23 +0800
commit51a8a7c2e3cc0730831963651a55d23d1fae624d (patch)
tree67583e907a2cadef4a983a2719a366e06bd2460a /ld
parent02dd9d25682311f45e1bb9629cbe4f6727e245a8 (diff)
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RISC-V: Fix that IRELATIVE relocs may be inserted to the wrong place.
For the ifunc symbol, which is referenced by GOT rather than PLT relocs, we should add the dynamic reloc (usually IRELATIVE) into the .rel.iplt when generating the static executable. But if we use riscv_elf_append_rela to add the dynamic relocs into .rela.iplt, this may cause the overwrite problem. The reason is that we don't handle the `reloc_index` of .rela.iplt, but the riscv_elf_append_rela adds the relocs to the place that are calculated from the reloc_index (in seqential). Therefore, we may overwrite the dynamic relocs when the `reloc_index` of .rela.iplt isn't handled correctly. One solution is that we can add these dynamic relocs (GOT ifunc) from the last of .rela.iplt section. But I'm not sure if it is the best way. bfd/ * elfnn-riscv.c (riscv_elf_link_hash_table): Add last_iplt_index. (riscv_elf_size_dynamic_sections): Initialize the last_iplt_index. (riscv_elf_relocate_section): Use riscv_elf_append_rela. (riscv_elf_finish_dynamic_symbol): If the use_elf_append_rela is false, then we should add the dynamic relocs from the last of the .rela.iplt, and don't use the riscv_elf_append_rela to add. ld/ * testsuite/ld-riscv-elf/ifunc-plt-got-overwrite.s: New testcase. * testsuite/ld-riscv-elf/ifunc-plt-got-overwrite.d: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-got-overwrite-exe.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-got-overwrite-pic.rd: Likewise. * testsuite/ld-riscv-elf/ifunc-plt-got-overwrite-pie.rd: Likewise. * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
Diffstat (limited to 'ld')
-rw-r--r--ld/ChangeLog9
-rw-r--r--ld/testsuite/ld-riscv-elf/ifunc-plt-got-overwrite-exe.rd4
-rw-r--r--ld/testsuite/ld-riscv-elf/ifunc-plt-got-overwrite-pic.rd8
-rw-r--r--ld/testsuite/ld-riscv-elf/ifunc-plt-got-overwrite-pie.rd7
-rw-r--r--ld/testsuite/ld-riscv-elf/ifunc-plt-got-overwrite.d19
-rw-r--r--ld/testsuite/ld-riscv-elf/ifunc-plt-got-overwrite.s38
-rw-r--r--ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp7
7 files changed, 92 insertions, 0 deletions
diff --git a/ld/ChangeLog b/ld/ChangeLog
index 3a9d381..780bb4b 100644
--- a/ld/ChangeLog
+++ b/ld/ChangeLog
@@ -1,5 +1,14 @@
2020-10-16 Nelson Chu <nelson.chu@sifive.com>
+ * testsuite/ld-riscv-elf/ifunc-plt-got-overwrite.s: New testcase.
+ * testsuite/ld-riscv-elf/ifunc-plt-got-overwrite.d: Likewise.
+ * testsuite/ld-riscv-elf/ifunc-plt-got-overwrite-exe.rd: Likewise.
+ * testsuite/ld-riscv-elf/ifunc-plt-got-overwrite-pic.rd: Likewise.
+ * testsuite/ld-riscv-elf/ifunc-plt-got-overwrite-pie.rd: Likewise.
+ * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
+
+2020-10-16 Nelson Chu <nelson.chu@sifive.com>
+
* emulparams/elf32lriscv-defs.sh: Add IREL_IN_PLT.
* testsuite/ld-ifunc/ifunc.exp: Enable ifunc tests for RISC-V.
* testsuite/ld-riscv-elf/ld-riscv-elf.exp (run_dump_test_ifunc):
diff --git a/ld/testsuite/ld-riscv-elf/ifunc-plt-got-overwrite-exe.rd b/ld/testsuite/ld-riscv-elf/ifunc-plt-got-overwrite-exe.rd
new file mode 100644
index 0000000..0de47a4
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/ifunc-plt-got-overwrite-exe.rd
@@ -0,0 +1,4 @@
+Relocation section '.rela.plt' at .*
+[ ]+Offset[ ]+Info[ ]+Type[ ]+.*
+[0-9a-f]+[ ]+[0-9a-f]+[ ]+R_RISCV_IRELATIVE[ ]+[0-9a-f]*
+[0-9a-f]+[ ]+[0-9a-f]+[ ]+R_RISCV_IRELATIVE[ ]+[0-9a-f]*
diff --git a/ld/testsuite/ld-riscv-elf/ifunc-plt-got-overwrite-pic.rd b/ld/testsuite/ld-riscv-elf/ifunc-plt-got-overwrite-pic.rd
new file mode 100644
index 0000000..f65d789
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/ifunc-plt-got-overwrite-pic.rd
@@ -0,0 +1,8 @@
+Relocation section '.rela.got' at .*
+[ ]+Offset[ ]+Info[ ]+Type[ ]+.*
+[0-9a-f]+[ ]+[0-9a-f]+[ ]+R_RISCV_(32|64)[ ]+foo2\(\)[ ]+foo2 \+ 0
+[0-9a-f]+[ ]+[0-9a-f]+[ ]+R_RISCV_(32|64)[ ]+foo1\(\)[ ]+foo1 \+ 0
+#...
+Relocation section '.rela.plt' at .*
+[ ]+Offset[ ]+Info[ ]+Type[ ]+.*
+[0-9a-f]+[ ]+[0-9a-f]+[ ]+R_RISCV_JUMP_SLOT[ ]+foo1\(\)[ ]+foo1 \+ 0
diff --git a/ld/testsuite/ld-riscv-elf/ifunc-plt-got-overwrite-pie.rd b/ld/testsuite/ld-riscv-elf/ifunc-plt-got-overwrite-pie.rd
new file mode 100644
index 0000000..32e66f0
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/ifunc-plt-got-overwrite-pie.rd
@@ -0,0 +1,7 @@
+Relocation section '.rela.got' at .*
+[ ]+Offset[ ]+Info[ ]+Type[ ]+.*
+[0-9a-f]+[ ]+[0-9a-f]+[ ]+R_RISCV_IRELATIVE[ ]+[0-9a-f]*
+
+Relocation section '.rela.plt' at .*
+[ ]+Offset[ ]+Info[ ]+Type[ ]+.*
+[0-9a-f]+[ ]+[0-9a-f]+[ ]+R_RISCV_IRELATIVE[ ]+[0-9a-f]*
diff --git a/ld/testsuite/ld-riscv-elf/ifunc-plt-got-overwrite.d b/ld/testsuite/ld-riscv-elf/ifunc-plt-got-overwrite.d
new file mode 100644
index 0000000..333dea3
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/ifunc-plt-got-overwrite.d
@@ -0,0 +1,19 @@
+#...
+Disassembly of section .plt:
+#...
+0+[0-9a-f]+ <(\*ABS\*\+0x[0-9a-f]+@plt|foo@plt|.plt)>:
+#...
+Disassembly of section .text:
+#...
+0+[0-9a-f]+ <foo_resolver>:
+#...
+0+[0-9a-f]+ <bar>:
+.*:[ ]+[0-9a-f]+[ ]+auipc[ ]+.*
+.*:[ ]+[0-9a-f]+[ ]+(lw|ld)[ ]+.*<(_GLOBAL_OFFSET_TABLE_.*|.*)>
+.*:[ ]+[0-9a-f]+[ ]+auipc[ ]+.*
+.*:[ ]+[0-9a-f]+[ ]+jalr[ ]+.*<(.*plt.*)>
+.*:[ ]+[0-9a-f]+[ ]+auipc[ ]+.*
+.*:[ ]+[0-9a-f]+[ ]+jalr[ ]+.*<(.*plt.*)>
+.*:[ ]+[0-9a-f]+[ ]+auipc[ ]+.*
+.*:[ ]+[0-9a-f]+[ ]+(lw|ld)[ ]+.*<(_GLOBAL_OFFSET_TABLE_.*|.*)>
+#...
diff --git a/ld/testsuite/ld-riscv-elf/ifunc-plt-got-overwrite.s b/ld/testsuite/ld-riscv-elf/ifunc-plt-got-overwrite.s
new file mode 100644
index 0000000..6c2f8e8
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/ifunc-plt-got-overwrite.s
@@ -0,0 +1,38 @@
+ .text
+
+ .type foo_resolver, @function
+foo_resolver:
+ ret
+ .size foo_resolver, .-foo_resolver
+
+ .globl foo1
+ .type foo1, %gnu_indirect_function
+ .set foo1, foo_resolver
+
+ .globl foo2
+ .type foo2, %gnu_indirect_function
+ .set foo2, foo_resolver
+
+ .globl bar
+ .type bar, @function
+bar:
+.L1:
+ auipc x1, %got_pcrel_hi (foo1)
+.ifdef __64_bit__
+ ld x1, %pcrel_lo (.L1) (x1)
+.else
+ lw x1, %pcrel_lo (.L1) (x1)
+.endif
+
+ call foo1
+ call foo1@plt
+
+.L2:
+ auipc x2, %got_pcrel_hi (foo2)
+.ifdef __64_bit__
+ ld x2, %pcrel_lo (.L2) (x2)
+.else
+ lw x2, %pcrel_lo (.L2) (x2)
+.endif
+ ret
+ .size bar, .-bar
diff --git a/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
index b82e092..9834041 100644
--- a/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
+++ b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
@@ -175,6 +175,13 @@ if [istarget "riscv*-*-*"] {
run_dump_test_ifunc "ifunc-plt-02" rv64 exe
run_dump_test_ifunc "ifunc-plt-02" rv64 pie
run_dump_test_ifunc "ifunc-plt-02" rv64 pic
+ # Check the .rela.iplt overwrite issue.
+ run_dump_test_ifunc "ifunc-plt-got-overwrite" rv32 exe
+ run_dump_test_ifunc "ifunc-plt-got-overwrite" rv32 pie
+ run_dump_test_ifunc "ifunc-plt-got-overwrite" rv32 pic
+ run_dump_test_ifunc "ifunc-plt-got-overwrite" rv64 exe
+ run_dump_test_ifunc "ifunc-plt-got-overwrite" rv64 pie
+ run_dump_test_ifunc "ifunc-plt-got-overwrite" rv64 pic
# Setup shared libraries.
run_ld_link_tests {