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authorNelson Chu <nelson.chu@sifive.com>2020-08-18 17:48:34 +0800
committerNelson Chu <nelson.chu@sifive.com>2020-09-03 11:11:51 +0800
commit32f0ce4db98eb1e8e1cc326d3a22ef0c436ae6fe (patch)
treed20388d7924e00b1f98f0ddf41711e4c927768eb /ld
parent72bd6912ea38224481f8bd0ed13b751e0fda4683 (diff)
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RISC-V: Report warnings rather than errors for the mis-matched ISA versions.
Same as the privileged spec attributes check - different ISA versions should be compatible, unless there are some known conflicts. Therefore, we should allow to link objects with different ISA versions, and update the output ISA versions once the corresponding input ones are newer. But it's better to also warn people that the conflicts may happen when the ISA versions are mis-matched. bfd/ * elfnn-riscv.c (riscv_version_mismatch): Change the return type from void to bfd_boolean. Report warnings rather than errors when the ISA versions are mis-matched. Afterwards, remember to update the output ISA versions to the newest ones. (riscv_merge_std_ext): Allow to link objects with different standard ISA versions. Try to add output ISA versions to merged_subsets first. (riscv_merge_multi_letter_ext): Likewise. But for standard additional ISA and non-standard ISA versions. ld/ * testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d: Update the message from error to warning. * testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d: New testcases. * testsuite/ld-riscv-elf/attr-merge-arch-failed-02a.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-failed-02b.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-failed-02c.s: Likewise. * testsuite/ld-riscv-elf/attr-merge-arch-failed-02d.s: Likewise. * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
Diffstat (limited to 'ld')
-rw-r--r--ld/ChangeLog11
-rw-r--r--ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d8
-rw-r--r--ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d27
-rw-r--r--ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-02a.s1
-rw-r--r--ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-02b.s1
-rw-r--r--ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-02c.s1
-rw-r--r--ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-02d.s1
-rw-r--r--ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp1
8 files changed, 50 insertions, 1 deletions
diff --git a/ld/ChangeLog b/ld/ChangeLog
index 4bba884..185f37b 100644
--- a/ld/ChangeLog
+++ b/ld/ChangeLog
@@ -1,3 +1,14 @@
+2020-09-03 Nelson Chu <nelson.chu@sifive.com>
+
+ * testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d: Update the
+ message from error to warning.
+ * testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d: New testcases.
+ * testsuite/ld-riscv-elf/attr-merge-arch-failed-02a.s: Likewise.
+ * testsuite/ld-riscv-elf/attr-merge-arch-failed-02b.s: Likewise.
+ * testsuite/ld-riscv-elf/attr-merge-arch-failed-02c.s: Likewise.
+ * testsuite/ld-riscv-elf/attr-merge-arch-failed-02d.s: Likewise.
+ * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Updated.
+
2020-09-03 Kito Cheng <kito.cheng@sifive.com>
* testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d: Updated.
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d
index 8a9c092..4b31238 100644
--- a/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-01.d
@@ -2,4 +2,10 @@
#source: attr-merge-arch-failed-01b.s
#as: -march-attr
#ld: -r -melf32lriscv
-#error: Mis-matched ISA version for 'a' extension. 3.0 vs 2.0
+#warning: .*mis-matched ISA version 3.0 for 'a' extension, the output version is 2.0
+#readelf: -A
+
+Attribute Section: riscv
+File Attributes
+ Tag_RISCV_arch: ".*a3p0.*"
+#..
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d
new file mode 100644
index 0000000..880ee15
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-02.d
@@ -0,0 +1,27 @@
+#source: attr-merge-arch-failed-02a.s
+#source: attr-merge-arch-failed-02b.s
+#source: attr-merge-arch-failed-02c.s
+#source: attr-merge-arch-failed-02d.s
+#as: -march-attr
+#ld: -r -melf32lriscv
+#warning: .*mis-matched ISA version 3.0 for 'i' extension, the output version is 2.0
+#warning: .*mis-matched ISA version 3.0 for 'm' extension, the output version is 2.0
+#warning: .*mis-matched ISA version 3.0 for 'a' extension, the output version is 2.0
+#warning: .*mis-matched ISA version 3.0 for 'zicsr' extension, the output version is 2.0
+#warning: .*mis-matched ISA version 3.0 for 'xunknown' extension, the output version is 2.0
+#warning: .*mis-matched ISA version 2.1 for 'i' extension, the output version is 3.0
+#warning: .*mis-matched ISA version 2.2 for 'm' extension, the output version is 3.0
+#warning: .*mis-matched ISA version 2.3 for 'a' extension, the output version is 3.0
+#warning: .*mis-matched ISA version 2.4 for 'zicsr' extension, the output version is 3.0
+#warning: .*mis-matched ISA version 2.5 for 'xunknown' extension, the output version is 3.0
+#warning: .*mis-matched ISA version 4.6 for 'i' extension, the output version is 3.0
+#warning: .*mis-matched ISA version 4.7 for 'm' extension, the output version is 3.0
+#warning: .*mis-matched ISA version 4.8 for 'a' extension, the output version is 3.0
+#warning: .*mis-matched ISA version 4.9 for 'zicsr' extension, the output version is 3.0
+#warning: .*mis-matched ISA version 4.0 for 'xunknown' extension, the output version is 3.0
+#readelf: -A
+
+Attribute Section: riscv
+File Attributes
+ Tag_RISCV_arch: "rv32i4p6_m4p7_a4p8_zicsr4p9_xunknown4p0"
+#..
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-02a.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-02a.s
new file mode 100644
index 0000000..3dbf8a2
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-02a.s
@@ -0,0 +1 @@
+ .attribute arch, "rv32i2p0_m2p0_a2p0_zicsr2p0_xunknown2p0"
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-02b.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-02b.s
new file mode 100644
index 0000000..7bbc39f
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-02b.s
@@ -0,0 +1 @@
+ .attribute arch, "rv32i3p0_m3p0_a3p0_zicsr3p0_xunknown3p0"
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-02c.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-02c.s
new file mode 100644
index 0000000..2a921e6
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-02c.s
@@ -0,0 +1 @@
+ .attribute arch, "rv32i2p1_m2p2_a2p3_zicsr2p4_xunknown2p5"
diff --git a/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-02d.s b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-02d.s
new file mode 100644
index 0000000..6ef5ee5
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/attr-merge-arch-failed-02d.s
@@ -0,0 +1 @@
+ .attribute arch, "rv32i4p6_m4p7_a4p8_zicsr4p9_xunknown4p0"
diff --git a/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
index 1a0c68f..2c008d4 100644
--- a/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
+++ b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
@@ -39,6 +39,7 @@ if [istarget "riscv*-*-*"] {
run_dump_test "attr-merge-priv-spec-02"
run_dump_test "attr-merge-priv-spec-03"
run_dump_test "attr-merge-arch-failed-01"
+ run_dump_test "attr-merge-arch-failed-02"
run_dump_test "attr-merge-stack-align-failed"
run_dump_test "attr-merge-priv-spec-failed-01"
run_dump_test "attr-merge-priv-spec-failed-02"