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authorAlan Modra <amodra@gmail.com>2019-06-23 12:28:39 +0930
committerAlan Modra <amodra@gmail.com>2019-06-23 23:11:27 +0930
commitbb22a41815facfaa3de621aad5d055eb8e477082 (patch)
treebd54a134f929ced282316e5a215330117f4bb728 /ld/testsuite/ld-powerpc
parent14b2a8e4244a29208ad430167860a0f01b20f215 (diff)
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PR24704, Internal error building skiboot for powerpc64-linux-gnu
While the skiboot linker script bears some culpability in this PR, it's also true that the GOT indirect to GOT relative optimisation for 16-bit offsets isn't safe. At least, it isn't safe to remove the GOT entry based on distance between the GOT pointer and symbol calculated from the preliminary layout. So this patch removes that optimisation, and reduces the range allowed for 32-bit and 34-bit offsets. PR 24704 bfd/ * elf64-ppc.c (R_PPC64_GOT16_DS): Don't set has_gotrel. (ppc64_elf_edit_toc): Don't remove R_PPC64_GOT16_DS got entries. Reduce range of offsets allowed for other GOT relocs. ld/ * testsuite/ld-powerpc/elfv2exe.d: Update. * testsuite/ld-powerpc/elfv2so.d: Update.
Diffstat (limited to 'ld/testsuite/ld-powerpc')
-rw-r--r--ld/testsuite/ld-powerpc/elfv2exe.d2
-rw-r--r--ld/testsuite/ld-powerpc/elfv2so.d12
2 files changed, 7 insertions, 7 deletions
diff --git a/ld/testsuite/ld-powerpc/elfv2exe.d b/ld/testsuite/ld-powerpc/elfv2exe.d
index 769f846..0ccfcbf 100644
--- a/ld/testsuite/ld-powerpc/elfv2exe.d
+++ b/ld/testsuite/ld-powerpc/elfv2exe.d
@@ -34,7 +34,7 @@ Disassembly of section \.text:
.*: (e8 62 80 08|08 80 62 e8) ld r3,-32760\(r2\)
.*: (4b .. .. ..|.. .. .. 4b) bl .*\.plt_branch\.f2>
.*: (60 00 00 00|00 00 00 60) nop
-.*: (38 62 80 10|10 80 62 38) addi r3,r2,-32752
+.*: (38 62 80 18|18 80 62 38) addi r3,r2,-32744
.*: (48 .. .. ..|.. .. .. 48) bl 10008888 <f3>
.*: (60 00 00 00|00 00 00 60) nop
.*: (4b .. .. ..|.. .. .. 4b) bl .*\.plt_branch\.f4>
diff --git a/ld/testsuite/ld-powerpc/elfv2so.d b/ld/testsuite/ld-powerpc/elfv2so.d
index 081eb49..0162bd0 100644
--- a/ld/testsuite/ld-powerpc/elfv2so.d
+++ b/ld/testsuite/ld-powerpc/elfv2so.d
@@ -9,35 +9,35 @@ Disassembly of section \.text:
.* <.*\.plt_call\.f4>:
.*: (f8 41 00 18|18 00 41 f8) std r2,24\(r1\)
-.*: (e9 82 80 38|38 80 82 e9) ld r12,-32712\(r2\)
+.*: (e9 82 80 40|40 80 82 e9) ld r12,-32704\(r2\)
.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
.*: (4e 80 04 20|20 04 80 4e) bctr
\.\.\.
.* <.*\.plt_call\.f3>:
.*: (f8 41 00 18|18 00 41 f8) std r2,24\(r1\)
-.*: (e9 82 80 28|28 80 82 e9) ld r12,-32728\(r2\)
+.*: (e9 82 80 30|30 80 82 e9) ld r12,-32720\(r2\)
.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
.*: (4e 80 04 20|20 04 80 4e) bctr
\.\.\.
.* <.*\.plt_call\.f5>:
.*: (f8 41 00 18|18 00 41 f8) std r2,24\(r1\)
-.*: (e9 82 80 20|20 80 82 e9) ld r12,-32736\(r2\)
+.*: (e9 82 80 28|28 80 82 e9) ld r12,-32728\(r2\)
.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
.*: (4e 80 04 20|20 04 80 4e) bctr
\.\.\.
.* <.*\.plt_call\.f1>:
.*: (f8 41 00 18|18 00 41 f8) std r2,24\(r1\)
-.*: (e9 82 80 40|40 80 82 e9) ld r12,-32704\(r2\)
+.*: (e9 82 80 48|48 80 82 e9) ld r12,-32696\(r2\)
.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
.*: (4e 80 04 20|20 04 80 4e) bctr
\.\.\.
.* <.*\.plt_call\.f2>:
.*: (f8 41 00 18|18 00 41 f8) std r2,24\(r1\)
-.*: (e9 82 80 30|30 80 82 e9) ld r12,-32720\(r2\)
+.*: (e9 82 80 38|38 80 82 e9) ld r12,-32712\(r2\)
.*: (7d 89 03 a6|a6 03 89 7d) mtctr r12
.*: (4e 80 04 20|20 04 80 4e) bctr
\.\.\.
@@ -52,7 +52,7 @@ Disassembly of section \.text:
.*: (e8 62 80 08|08 80 62 e8) ld r3,-32760\(r2\)
.*: (4b .. .. ..|.. .. .. 4b) bl .*\.plt_call\.f2>
.*: (e8 41 00 18|18 00 41 e8) ld r2,24\(r1\)
-.*: (38 62 80 48|48 80 62 38) addi r3,r2,-32696
+.*: (38 62 80 50|50 80 62 38) addi r3,r2,-32688
.*: (4b .. .. ..|.. .. .. 4b) bl .*\.plt_call\.f3>
.*: (e8 41 00 18|18 00 41 e8) ld r2,24\(r1\)
.*: (4b .. .. ..|.. .. .. 4b) bl .*\.plt_call\.f4>