* ld-mips-elf/reloc-1[ab].s: New source files.

	* ld-mips-elf/reloc-1-{n32,n64,rel}.d: New tests.
	* ld-mips-elf/reloc-2[ab].s: New source files.
	* ld-mips-elf/reloc-2.{d,ld}: New test.
	* ld-mips-elf/reloc-3[ab].s: New source files.
	* ld-mips-elf/reloc-3-{r,srec}.d: New tests.
	* ld-mips-elf/mips-elf.exp: Run them.

15 files changed, 1797 insertions, 0 deletions

diff --git a/ld/testsuite/ld-mips-elf/mips-elf.exp b/ld/testsuite/ld-mips-elf/mips-elf.exp
index 96739fa..f2194a1 100644
--- a/ld/testsuite/ld-mips-elf/mips-elf.exp
+++ b/ld/testsuite/ld-mips-elf/mips-elf.exp
@@ -79,3 +79,21 @@ if { $embedded_elf } {
 
     run_dump_test "region1"
 }
+
+if $embedded_elf {
+    # This could work on other targets too, but would need the appropriate
+    # ld -m switch.
+    run_dump_test "reloc-1-rel"
+}
+if $has_newabi {
+    run_dump_test "reloc-1-n32"
+    if $linux_gnu {
+	# Uses a linux-specific ld -m switch
+	run_dump_test "reloc-1-n64"
+    }
+}
+run_dump_test "reloc-2"
+if $embedded_elf {
+    run_dump_test "reloc-3-r"
+    run_dump_test "reloc-3-srec"
+}
diff --git a/ld/testsuite/ld-mips-elf/reloc-1-n32.d b/ld/testsuite/ld-mips-elf/reloc-1-n32.d
new file mode 100644
index 0000000..dd41822
--- /dev/null
+++ b/ld/testsuite/ld-mips-elf/reloc-1-n32.d
@@ -0,0 +1,199 @@
+#source: reloc-1a.s -mabi=n32
+#source: reloc-1b.s -mabi=n32
+#ld: -r
+#readelf: --relocs
+
+Relocation section '\.rela\.text' .*
+.*
+#
+# Relocations against tstarta
+#
+.* R_MIPS_HI16 .* \.text \+ ffff7ff0
+.* R_MIPS_LO16 .* \.text \+ ffff7ff0
+.* R_MIPS_HI16 .* \.text \+ ffff8000
+.* R_MIPS_LO16 .* \.text \+ ffff8000
+.* R_MIPS_HI16 .* \.text \+ 0
+.* R_MIPS_LO16 .* \.text \+ 0
+.* R_MIPS_HI16 .* \.text \+ 7ff0
+.* R_MIPS_LO16 .* \.text \+ 7ff0
+.* R_MIPS_HI16 .* \.text \+ 8010
+.* R_MIPS_LO16 .* \.text \+ 8010
+#
+# Relocations against t32a
+#
+.* R_MIPS_HI16 .* \.text \+ ffff8010
+.* R_MIPS_LO16 .* \.text \+ ffff8010
+.* R_MIPS_HI16 .* \.text \+ ffff8020
+.* R_MIPS_LO16 .* \.text \+ ffff8020
+.* R_MIPS_HI16 .* \.text \+ 20
+.* R_MIPS_LO16 .* \.text \+ 20
+.* R_MIPS_HI16 .* \.text \+ 8010
+.* R_MIPS_LO16 .* \.text \+ 8010
+.* R_MIPS_HI16 .* \.text \+ 8030
+.* R_MIPS_LO16 .* \.text \+ 8030
+#
+# Relocations against _start
+#
+.* R_MIPS_HI16 .* _start \+ ffff7ff0
+.* R_MIPS_LO16 .* _start \+ ffff7ff0
+.* R_MIPS_HI16 .* _start \+ ffff8000
+.* R_MIPS_LO16 .* _start \+ ffff8000
+.* R_MIPS_HI16 .* _start \+ 0
+.* R_MIPS_LO16 .* _start \+ 0
+.* R_MIPS_HI16 .* _start \+ 7ff0
+.* R_MIPS_LO16 .* _start \+ 7ff0
+.* R_MIPS_HI16 .* _start \+ 8010
+.* R_MIPS_LO16 .* _start \+ 8010
+#
+# Relocations against tstarta
+#
+.* R_MIPS_GOT16 .* \.text \+ ffff7ff0
+.* R_MIPS_LO16 .* \.text \+ ffff7ff0
+.* R_MIPS_GOT16 .* \.text \+ ffff8000
+.* R_MIPS_LO16 .* \.text \+ ffff8000
+.* R_MIPS_GOT16 .* \.text \+ 0
+.* R_MIPS_LO16 .* \.text \+ 0
+.* R_MIPS_GOT16 .* \.text \+ 7ff0
+.* R_MIPS_LO16 .* \.text \+ 7ff0
+.* R_MIPS_GOT16 .* \.text \+ 8010
+.* R_MIPS_LO16 .* \.text \+ 8010
+#
+# Relocations against t32a
+#
+.* R_MIPS_GOT16 .* \.text \+ ffff8010
+.* R_MIPS_LO16 .* \.text \+ ffff8010
+.* R_MIPS_GOT16 .* \.text \+ ffff8020
+.* R_MIPS_LO16 .* \.text \+ ffff8020
+.* R_MIPS_GOT16 .* \.text \+ 20
+.* R_MIPS_LO16 .* \.text \+ 20
+.* R_MIPS_GOT16 .* \.text \+ 8010
+.* R_MIPS_LO16 .* \.text \+ 8010
+.* R_MIPS_GOT16 .* \.text \+ 8030
+.* R_MIPS_LO16 .* \.text \+ 8030
+#
+# Relocations against sdg
+#
+.* R_MIPS_GPREL16 .* sdg \+ fffffffc
+.* R_MIPS_GPREL16 .* sdg \+ 0
+.* R_MIPS_GPREL16 .* sdg \+ 4
+#
+# Relocations against sdla.  .sdata should be the first piece of gp-relative
+# data, which the linker script should put _gp - 0x7ff0.
+#
+.* R_MIPS_GPREL16 .* \.sdata \+ ffff801c
+.* R_MIPS_GPREL16 .* \.sdata \+ ffff8020
+.* R_MIPS_GPREL16 .* \.sdata \+ ffff8024
+#
+# Relocations against tstarta
+#
+.* R_MIPS_26 .* \.text \+ fffffffc
+.* R_MIPS_26 .* \.text \+ 0
+.* R_MIPS_26 .* \.text \+ 4
+#
+# Relocations against t32a
+#
+.* R_MIPS_26 .* \.text \+ 1c
+.* R_MIPS_26 .* \.text \+ 20
+.* R_MIPS_26 .* \.text \+ 24
+#
+# Relocations against _start
+#
+.* R_MIPS_26 .* _start \+ fffffffc
+.* R_MIPS_26 .* _start \+ 0
+.* R_MIPS_26 .* _start \+ 4
+#
+# Relocations against tstartb
+#
+.* R_MIPS_HI16 .* \.text \+ 7fe0
+.* R_MIPS_LO16 .* \.text \+ 7fe0
+.* R_MIPS_HI16 .* \.text \+ 7ff0
+.* R_MIPS_LO16 .* \.text \+ 7ff0
+.* R_MIPS_HI16 .* \.text \+ fff0
+.* R_MIPS_LO16 .* \.text \+ fff0
+.* R_MIPS_HI16 .* \.text \+ 17fe0
+.* R_MIPS_LO16 .* \.text \+ 17fe0
+.* R_MIPS_HI16 .* \.text \+ 18000
+.* R_MIPS_LO16 .* \.text \+ 18000
+#
+# Relocations against t32b
+#
+.* R_MIPS_HI16 .* \.text \+ 8000
+.* R_MIPS_LO16 .* \.text \+ 8000
+.* R_MIPS_HI16 .* \.text \+ 8010
+.* R_MIPS_LO16 .* \.text \+ 8010
+.* R_MIPS_HI16 .* \.text \+ 10010
+.* R_MIPS_LO16 .* \.text \+ 10010
+.* R_MIPS_HI16 .* \.text \+ 18000
+.* R_MIPS_LO16 .* \.text \+ 18000
+.* R_MIPS_HI16 .* \.text \+ 18020
+.* R_MIPS_LO16 .* \.text \+ 18020
+#
+# Relocations against _start
+#
+.* R_MIPS_HI16 .* _start \+ ffff7ff0
+.* R_MIPS_LO16 .* _start \+ ffff7ff0
+.* R_MIPS_HI16 .* _start \+ ffff8000
+.* R_MIPS_LO16 .* _start \+ ffff8000
+.* R_MIPS_HI16 .* _start \+ 0
+.* R_MIPS_LO16 .* _start \+ 0
+.* R_MIPS_HI16 .* _start \+ 7ff0
+.* R_MIPS_LO16 .* _start \+ 7ff0
+.* R_MIPS_HI16 .* _start \+ 8010
+.* R_MIPS_LO16 .* _start \+ 8010
+#
+# Relocations against tstartb
+#
+.* R_MIPS_GOT16 .* \.text \+ 7fe0
+.* R_MIPS_LO16 .* \.text \+ 7fe0
+.* R_MIPS_GOT16 .* \.text \+ 7ff0
+.* R_MIPS_LO16 .* \.text \+ 7ff0
+.* R_MIPS_GOT16 .* \.text \+ fff0
+.* R_MIPS_LO16 .* \.text \+ fff0
+.* R_MIPS_GOT16 .* \.text \+ 17fe0
+.* R_MIPS_LO16 .* \.text \+ 17fe0
+.* R_MIPS_GOT16 .* \.text \+ 18000
+.* R_MIPS_LO16 .* \.text \+ 18000
+#
+# Relocations against t32b
+#
+.* R_MIPS_GOT16 .* \.text \+ 8000
+.* R_MIPS_LO16 .* \.text \+ 8000
+.* R_MIPS_GOT16 .* \.text \+ 8010
+.* R_MIPS_LO16 .* \.text \+ 8010
+.* R_MIPS_GOT16 .* \.text \+ 10010
+.* R_MIPS_LO16 .* \.text \+ 10010
+.* R_MIPS_GOT16 .* \.text \+ 18000
+.* R_MIPS_LO16 .* \.text \+ 18000
+.* R_MIPS_GOT16 .* \.text \+ 18020
+.* R_MIPS_LO16 .* \.text \+ 18020
+#
+# Relocations against sdg
+#
+.* R_MIPS_GPREL16 .* sdg \+ fffffffc
+.* R_MIPS_GPREL16 .* sdg \+ 0
+.* R_MIPS_GPREL16 .* sdg \+ 4
+#
+# Relocations against sdlb
+#
+.* R_MIPS_GPREL16 .* \.sdata \+ ffff803c
+.* R_MIPS_GPREL16 .* \.sdata \+ ffff8040
+.* R_MIPS_GPREL16 .* \.sdata \+ ffff8044
+#
+# Relocations against tstartb
+#
+.* R_MIPS_26 .* \.text \+ ffec
+.* R_MIPS_26 .* \.text \+ fff0
+.* R_MIPS_26 .* \.text \+ fff4
+#
+# Relocations against t32b
+#
+.* R_MIPS_26 .* \.text \+ 1000c
+.* R_MIPS_26 .* \.text \+ 10010
+.* R_MIPS_26 .* \.text \+ 10014
+#
+# Relocations against _start
+#
+.* R_MIPS_26 .* _start \+ fffffffc
+.* R_MIPS_26 .* _start \+ 0
+.* R_MIPS_26 .* _start \+ 4
+#pass
diff --git a/ld/testsuite/ld-mips-elf/reloc-1-n64.d b/ld/testsuite/ld-mips-elf/reloc-1-n64.d
new file mode 100644
index 0000000..2db8fca
--- /dev/null
+++ b/ld/testsuite/ld-mips-elf/reloc-1-n64.d
@@ -0,0 +1,459 @@
+#source: reloc-1a.s -mabi=64 -EB
+#source: reloc-1b.s -mabi=64 -EB
+#ld: -melf64btsmip -r
+#readelf: --relocs
+
+Relocation section '\.rela\.text' .*
+.*
+#
+# Relocations against tstarta
+#
+.* R_MIPS_HI16 .* \.text \+ ffff7ff0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ ffff7ff0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_HI16 .* \.text \+ ffff8000
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ ffff8000
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_HI16 .* \.text \+ 0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_HI16 .* \.text \+ 7ff0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 7ff0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_HI16 .* \.text \+ 8010
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 8010
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+#
+# Relocations against t32a
+#
+.* R_MIPS_HI16 .* \.text \+ ffff8010
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ ffff8010
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_HI16 .* \.text \+ ffff8020
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ ffff8020
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_HI16 .* \.text \+ 20
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 20
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_HI16 .* \.text \+ 8010
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 8010
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_HI16 .* \.text \+ 8030
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 8030
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+#
+# Relocations against _start
+#
+.* R_MIPS_HI16 .* _start \+ ffff7ff0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* _start \+ ffff7ff0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_HI16 .* _start \+ ffff8000
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* _start \+ ffff8000
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_HI16 .* _start \+ 0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* _start \+ 0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_HI16 .* _start \+ 7ff0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* _start \+ 7ff0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_HI16 .* _start \+ 8010
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* _start \+ 8010
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+#
+# Relocations against tstarta
+#
+.* R_MIPS_GOT16 .* \.text \+ ffff7ff0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ ffff7ff0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_GOT16 .* \.text \+ ffff8000
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ ffff8000
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_GOT16 .* \.text \+ 0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_GOT16 .* \.text \+ 7ff0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 7ff0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_GOT16 .* \.text \+ 8010
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 8010
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+#
+# Relocations against t32a
+#
+.* R_MIPS_GOT16 .* \.text \+ ffff8010
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ ffff8010
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_GOT16 .* \.text \+ ffff8020
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ ffff8020
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_GOT16 .* \.text \+ 20
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 20
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_GOT16 .* \.text \+ 8010
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 8010
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_GOT16 .* \.text \+ 8030
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 8030
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+#
+# Relocations against sdg
+#
+.* R_MIPS_GPREL16 .* sdg \+ fffffffc
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_GPREL16 .* sdg \+ 0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_GPREL16 .* sdg \+ 4
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+#
+# Relocations against sdla.  .sdata should be the first piece of gp-relative
+# data, which the linker script should put _gp - 0x7ff0.
+#
+.* R_MIPS_GPREL16 .* \.sdata \+ ffff801c
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_GPREL16 .* \.sdata \+ ffff8020
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_GPREL16 .* \.sdata \+ ffff8024
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+#
+# Relocations against tstarta
+#
+.* R_MIPS_26 .* \.text \+ fffffffc
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_26 .* \.text \+ 0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_26 .* \.text \+ 4
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+#
+# Relocations against t32a
+#
+.* R_MIPS_26 .* \.text \+ 1c
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_26 .* \.text \+ 20
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_26 .* \.text \+ 24
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+#
+# Relocations against _start
+#
+.* R_MIPS_26 .* _start \+ fffffffc
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_26 .* _start \+ 0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_26 .* _start \+ 4
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+#
+# Relocations against tstartb
+#
+.* R_MIPS_HI16 .* \.text \+ 7fe0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 7fe0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_HI16 .* \.text \+ 7ff0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 7ff0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_HI16 .* \.text \+ fff0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ fff0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_HI16 .* \.text \+ 17fe0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 17fe0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_HI16 .* \.text \+ 18000
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 18000
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+#
+# Relocations against t32b
+#
+.* R_MIPS_HI16 .* \.text \+ 8000
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 8000
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_HI16 .* \.text \+ 8010
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 8010
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_HI16 .* \.text \+ 10010
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 10010
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_HI16 .* \.text \+ 18000
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 18000
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_HI16 .* \.text \+ 18020
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 18020
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+#
+# Relocations against _start
+#
+.* R_MIPS_HI16 .* _start \+ ffff7ff0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* _start \+ ffff7ff0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_HI16 .* _start \+ ffff8000
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* _start \+ ffff8000
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_HI16 .* _start \+ 0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* _start \+ 0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_HI16 .* _start \+ 7ff0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* _start \+ 7ff0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_HI16 .* _start \+ 8010
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* _start \+ 8010
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+#
+# Relocations against tstartb
+#
+.* R_MIPS_GOT16 .* \.text \+ 7fe0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 7fe0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_GOT16 .* \.text \+ 7ff0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 7ff0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_GOT16 .* \.text \+ fff0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ fff0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_GOT16 .* \.text \+ 17fe0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 17fe0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_GOT16 .* \.text \+ 18000
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 18000
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+#
+# Relocations against t32b
+#
+.* R_MIPS_GOT16 .* \.text \+ 8000
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 8000
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_GOT16 .* \.text \+ 8010
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 8010
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_GOT16 .* \.text \+ 10010
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 10010
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_GOT16 .* \.text \+ 18000
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 18000
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_GOT16 .* \.text \+ 18020
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_LO16 .* \.text \+ 18020
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+#
+# Relocations against sdg
+#
+.* R_MIPS_GPREL16 .* sdg \+ fffffffc
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_GPREL16 .* sdg \+ 0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_GPREL16 .* sdg \+ 4
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+#
+# Relocations against sdlb
+#
+.* R_MIPS_GPREL16 .* \.sdata \+ ffff803c
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_GPREL16 .* \.sdata \+ ffff8040
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_GPREL16 .* \.sdata \+ ffff8044
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+#
+# Relocations against tstartb
+#
+.* R_MIPS_26 .* \.text \+ ffec
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_26 .* \.text \+ fff0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_26 .* \.text \+ fff4
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+#
+# Relocations against t32b
+#
+.* R_MIPS_26 .* \.text \+ 1000c
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_26 .* \.text \+ 10010
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_26 .* \.text \+ 10014
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+#
+# Relocations against _start
+#
+.* R_MIPS_26 .* _start \+ fffffffc
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_26 .* _start \+ 0
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+.* R_MIPS_26 .* _start \+ 4
+.* R_MIPS_NONE *
+.* R_MIPS_NONE *
+#pass
diff --git a/ld/testsuite/ld-mips-elf/reloc-1-rel.d b/ld/testsuite/ld-mips-elf/reloc-1-rel.d
new file mode 100644
index 0000000..e37da1e
--- /dev/null
+++ b/ld/testsuite/ld-mips-elf/reloc-1-rel.d
@@ -0,0 +1,356 @@
+#source: reloc-1a.s
+#source: reloc-1b.s
+#ld: -r
+#objdump: -dr
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+.* <.*>:
+#
+# Relocations against tstarta
+#
+.*:	3c04ffff 	lui	a0,0xffff
+			.*: R_MIPS_HI16	\.text
+.*:	24847ff0 	addiu	a0,a0,32752
+			.*: R_MIPS_LO16	\.text
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_HI16	\.text
+.*:	24848000 	addiu	a0,a0,-32768
+			.*: R_MIPS_LO16	\.text
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_HI16	\.text
+.*:	24840000 	addiu	a0,a0,0
+			.*: R_MIPS_LO16	\.text
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_HI16	\.text
+.*:	24847ff0 	addiu	a0,a0,32752
+			.*: R_MIPS_LO16	\.text
+
+.* <t32a>:
+.*:	3c040001 	lui	a0,0x1
+			.*: R_MIPS_HI16	\.text
+.*:	24848010 	addiu	a0,a0,-32752
+			.*: R_MIPS_LO16	\.text
+#
+# Relocations against t32a
+#
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_HI16	\.text
+.*:	24848010 	addiu	a0,a0,-32752
+			.*: R_MIPS_LO16	\.text
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_HI16	\.text
+.*:	24848020 	addiu	a0,a0,-32736
+			.*: R_MIPS_LO16	\.text
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_HI16	\.text
+.*:	24840020 	addiu	a0,a0,32
+			.*: R_MIPS_LO16	\.text
+.*:	3c040001 	lui	a0,0x1
+			.*: R_MIPS_HI16	\.text
+.*:	24848010 	addiu	a0,a0,-32752
+			.*: R_MIPS_LO16	\.text
+.*:	3c040001 	lui	a0,0x1
+			.*: R_MIPS_HI16	\.text
+.*:	24848030 	addiu	a0,a0,-32720
+			.*: R_MIPS_LO16	\.text
+#
+# Relocations against _start
+#
+.*:	3c04ffff 	lui	a0,0xffff
+			.*: R_MIPS_HI16	_start
+.*:	24847ff0 	addiu	a0,a0,32752
+			.*: R_MIPS_LO16	_start
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_HI16	_start
+.*:	24848000 	addiu	a0,a0,-32768
+			.*: R_MIPS_LO16	_start
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_HI16	_start
+.*:	24840000 	addiu	a0,a0,0
+			.*: R_MIPS_LO16	_start
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_HI16	_start
+.*:	24847ff0 	addiu	a0,a0,32752
+			.*: R_MIPS_LO16	_start
+.*:	3c040001 	lui	a0,0x1
+			.*: R_MIPS_HI16	_start
+.*:	24848010 	addiu	a0,a0,-32752
+			.*: R_MIPS_LO16	_start
+#
+# Relocations against tstarta
+#
+.*:	3c04ffff 	lui	a0,0xffff
+			.*: R_MIPS_GOT16	\.text
+.*:	24847ff0 	addiu	a0,a0,32752
+			.*: R_MIPS_LO16	\.text
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_GOT16	\.text
+.*:	24848000 	addiu	a0,a0,-32768
+			.*: R_MIPS_LO16	\.text
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_GOT16	\.text
+.*:	24840000 	addiu	a0,a0,0
+			.*: R_MIPS_LO16	\.text
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_GOT16	\.text
+.*:	24847ff0 	addiu	a0,a0,32752
+			.*: R_MIPS_LO16	\.text
+.*:	3c040001 	lui	a0,0x1
+			.*: R_MIPS_GOT16	\.text
+.*:	24848010 	addiu	a0,a0,-32752
+			.*: R_MIPS_LO16	\.text
+#
+# Relocations against t32a
+#
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_GOT16	\.text
+.*:	24848010 	addiu	a0,a0,-32752
+			.*: R_MIPS_LO16	\.text
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_GOT16	\.text
+.*:	24848020 	addiu	a0,a0,-32736
+			.*: R_MIPS_LO16	\.text
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_GOT16	\.text
+.*:	24840020 	addiu	a0,a0,32
+			.*: R_MIPS_LO16	\.text
+.*:	3c040001 	lui	a0,0x1
+			.*: R_MIPS_GOT16	\.text
+.*:	24848010 	addiu	a0,a0,-32752
+			.*: R_MIPS_LO16	\.text
+.*:	3c040001 	lui	a0,0x1
+			.*: R_MIPS_GOT16	\.text
+.*:	24848030 	addiu	a0,a0,-32720
+			.*: R_MIPS_LO16	\.text
+#
+# Relocations against sdg
+#
+.*:	2484fffc 	addiu	a0,a0,-4
+			.*: R_MIPS_GPREL16	sdg
+.*:	24840000 	addiu	a0,a0,0
+			.*: R_MIPS_GPREL16	sdg
+.*:	24840004 	addiu	a0,a0,4
+			.*: R_MIPS_GPREL16	sdg
+#
+# Relocations against sdla
+#
+.*:	2484801c 	addiu	a0,a0,-32740
+			.*: R_MIPS_GPREL16	\.sdata\+0x7ff0
+.*:	24848020 	addiu	a0,a0,-32736
+			.*: R_MIPS_GPREL16	\.sdata\+0x7ff0
+.*:	24848024 	addiu	a0,a0,-32732
+			.*: R_MIPS_GPREL16	\.sdata\+0x7ff0
+#
+# Relocations against tstarta
+#
+.*:	0fffffff 	jal	.*
+			.*: R_MIPS_26	\.text
+.*:	00000000 	nop
+.*:	0c000000 	jal	.*
+			.*: R_MIPS_26	\.text
+.*:	00000000 	nop
+.*:	0c000001 	jal	.*
+			.*: R_MIPS_26	\.text
+.*:	00000000 	nop
+#
+# Relocations against t32a
+#
+.*:	0c000007 	jal	.*
+			.*: R_MIPS_26	\.text
+.*:	00000000 	nop
+.*:	0c000008 	jal	.*
+			.*: R_MIPS_26	\.text
+.*:	00000000 	nop
+.*:	0c000009 	jal	.*
+			.*: R_MIPS_26	\.text
+.*:	00000000 	nop
+#
+# Relocations against _start
+#
+.*:	0fffffff 	jal	.*
+			.*: R_MIPS_26	_start
+.*:	00000000 	nop
+.*:	0c000000 	jal	.*
+			.*: R_MIPS_26	_start
+.*:	00000000 	nop
+.*:	0c000001 	jal	.*
+			.*: R_MIPS_26	_start
+.*:	00000000 	nop
+	\.\.\.
+
+.* <tstartb>:
+#
+# Relocations against tstartb
+#
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_HI16	\.text
+.*:	24847fe0 	addiu	a0,a0,32736
+			.*: R_MIPS_LO16	\.text
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_HI16	\.text
+.*:	24847ff0 	addiu	a0,a0,32752
+			.*: R_MIPS_LO16	\.text
+.*:	3c040001 	lui	a0,0x1
+			.*: R_MIPS_HI16	\.text
+.*:	2484fff0 	addiu	a0,a0,-16
+			.*: R_MIPS_LO16	\.text
+.*:	3c040001 	lui	a0,0x1
+			.*: R_MIPS_HI16	\.text
+.*:	24847fe0 	addiu	a0,a0,32736
+			.*: R_MIPS_LO16	\.text
+
+.* <t32b>:
+.*:	3c040002 	lui	a0,0x2
+			.*: R_MIPS_HI16	\.text
+.*:	24848000 	addiu	a0,a0,-32768
+			.*: R_MIPS_LO16	\.text
+#
+# Relocations against t32b
+#
+.*:	3c040001 	lui	a0,0x1
+			.*: R_MIPS_HI16	\.text
+.*:	24848000 	addiu	a0,a0,-32768
+			.*: R_MIPS_LO16	\.text
+.*:	3c040001 	lui	a0,0x1
+			.*: R_MIPS_HI16	\.text
+.*:	24848010 	addiu	a0,a0,-32752
+			.*: R_MIPS_LO16	\.text
+.*:	3c040001 	lui	a0,0x1
+			.*: R_MIPS_HI16	\.text
+.*:	24840010 	addiu	a0,a0,16
+			.*: R_MIPS_LO16	\.text
+.*:	3c040002 	lui	a0,0x2
+			.*: R_MIPS_HI16	\.text
+.*:	24848000 	addiu	a0,a0,-32768
+			.*: R_MIPS_LO16	\.text
+.*:	3c040002 	lui	a0,0x2
+			.*: R_MIPS_HI16	\.text
+.*:	24848020 	addiu	a0,a0,-32736
+			.*: R_MIPS_LO16	\.text
+#
+# Relocations against _start
+#
+.*:	3c04ffff 	lui	a0,0xffff
+			.*: R_MIPS_HI16	_start
+.*:	24847ff0 	addiu	a0,a0,32752
+			.*: R_MIPS_LO16	_start
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_HI16	_start
+.*:	24848000 	addiu	a0,a0,-32768
+			.*: R_MIPS_LO16	_start
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_HI16	_start
+.*:	24840000 	addiu	a0,a0,0
+			.*: R_MIPS_LO16	_start
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_HI16	_start
+.*:	24847ff0 	addiu	a0,a0,32752
+			.*: R_MIPS_LO16	_start
+.*:	3c040001 	lui	a0,0x1
+			.*: R_MIPS_HI16	_start
+.*:	24848010 	addiu	a0,a0,-32752
+			.*: R_MIPS_LO16	_start
+#
+# Relocations against tstartb
+#
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_GOT16	\.text
+.*:	24847fe0 	addiu	a0,a0,32736
+			.*: R_MIPS_LO16	\.text
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_GOT16	\.text
+.*:	24847ff0 	addiu	a0,a0,32752
+			.*: R_MIPS_LO16	\.text
+.*:	3c040001 	lui	a0,0x1
+			.*: R_MIPS_GOT16	\.text
+.*:	2484fff0 	addiu	a0,a0,-16
+			.*: R_MIPS_LO16	\.text
+.*:	3c040001 	lui	a0,0x1
+			.*: R_MIPS_GOT16	\.text
+.*:	24847fe0 	addiu	a0,a0,32736
+			.*: R_MIPS_LO16	\.text
+.*:	3c040002 	lui	a0,0x2
+			.*: R_MIPS_GOT16	\.text
+.*:	24848000 	addiu	a0,a0,-32768
+			.*: R_MIPS_LO16	\.text
+#
+# Relocations against t32b
+#
+.*:	3c040001 	lui	a0,0x1
+			.*: R_MIPS_GOT16	\.text
+.*:	24848000 	addiu	a0,a0,-32768
+			.*: R_MIPS_LO16	\.text
+.*:	3c040001 	lui	a0,0x1
+			.*: R_MIPS_GOT16	\.text
+.*:	24848010 	addiu	a0,a0,-32752
+			.*: R_MIPS_LO16	\.text
+.*:	3c040001 	lui	a0,0x1
+			.*: R_MIPS_GOT16	\.text
+.*:	24840010 	addiu	a0,a0,16
+			.*: R_MIPS_LO16	\.text
+.*:	3c040002 	lui	a0,0x2
+			.*: R_MIPS_GOT16	\.text
+.*:	24848000 	addiu	a0,a0,-32768
+			.*: R_MIPS_LO16	\.text
+.*:	3c040002 	lui	a0,0x2
+			.*: R_MIPS_GOT16	\.text
+.*:	24848020 	addiu	a0,a0,-32736
+			.*: R_MIPS_LO16	\.text
+#
+# Relocations against sdg
+#
+.*:	2484fffc 	addiu	a0,a0,-4
+			.*: R_MIPS_GPREL16	sdg
+.*:	24840000 	addiu	a0,a0,0
+			.*: R_MIPS_GPREL16	sdg
+.*:	24840004 	addiu	a0,a0,4
+			.*: R_MIPS_GPREL16	sdg
+#
+# Relocations against sdlb
+#
+.*:	2484803c 	addiu	a0,a0,-32708
+			.*: R_MIPS_GPREL16	\.sdata\+0x7ff0
+.*:	24848040 	addiu	a0,a0,-32704
+			.*: R_MIPS_GPREL16	\.sdata\+0x7ff0
+.*:	24848044 	addiu	a0,a0,-32700
+			.*: R_MIPS_GPREL16	\.sdata\+0x7ff0
+#
+# Relocations against tstartb
+#
+.*:	0c003ffb 	jal	.*
+			.*: R_MIPS_26	\.text
+.*:	00000000 	nop
+.*:	0c003ffc 	jal	.*
+			.*: R_MIPS_26	\.text
+.*:	00000000 	nop
+.*:	0c003ffd 	jal	.*
+			.*: R_MIPS_26	\.text
+.*:	00000000 	nop
+#
+# Relocations against t32b
+#
+.*:	0c004003 	jal	.*
+			.*: R_MIPS_26	\.text
+.*:	00000000 	nop
+.*:	0c004004 	jal	.*
+			.*: R_MIPS_26	\.text
+.*:	00000000 	nop
+.*:	0c004005 	jal	.*
+			.*: R_MIPS_26	\.text
+.*:	00000000 	nop
+#
+# Relocations against _start
+#
+.*:	0fffffff 	jal	.*
+			.*: R_MIPS_26	_start
+.*:	00000000 	nop
+.*:	0c000000 	jal	.*
+			.*: R_MIPS_26	_start
+.*:	00000000 	nop
+.*:	0c000001 	jal	.*
+			.*: R_MIPS_26	_start
+.*:	00000000 	nop
+	\.\.\.
diff --git a/ld/testsuite/ld-mips-elf/reloc-1a.s b/ld/testsuite/ld-mips-elf/reloc-1a.s
new file mode 100644
index 0000000..5fcd4bb
--- /dev/null
+++ b/ld/testsuite/ld-mips-elf/reloc-1a.s
@@ -0,0 +1,100 @@
+	.globl	_start
+	.globl	sdg
+	.set	noreorder
+	.ent	tstarta
+tstarta:
+_start:
+	lui	$4,%hi(tstarta - 0x8010)
+	addiu	$4,$4,%lo(tstarta - 0x8010)
+	lui	$4,%hi(tstarta - 0x8000)
+	addiu	$4,$4,%lo(tstarta - 0x8000)
+	lui	$4,%hi(tstarta)
+	addiu	$4,$4,%lo(tstarta)
+	lui	$4,%hi(tstarta + 0x7ff0)
+	addiu	$4,$4,%lo(tstarta + 0x7ff0)
+t32a:
+	lui	$4,%hi(tstarta + 0x8010)
+	addiu	$4,$4,%lo(tstarta + 0x8010)
+
+	lui	$4,%hi(t32a - 0x8010)
+	addiu	$4,$4,%lo(t32a - 0x8010)
+	lui	$4,%hi(t32a - 0x8000)
+	addiu	$4,$4,%lo(t32a - 0x8000)
+	lui	$4,%hi(t32a)
+	addiu	$4,$4,%lo(t32a)
+	lui	$4,%hi(t32a + 0x7ff0)
+	addiu	$4,$4,%lo(t32a + 0x7ff0)
+	lui	$4,%hi(t32a + 0x8010)
+	addiu	$4,$4,%lo(t32a + 0x8010)
+
+	lui	$4,%hi(_start - 0x8010)
+	addiu	$4,$4,%lo(_start - 0x8010)
+	lui	$4,%hi(_start - 0x8000)
+	addiu	$4,$4,%lo(_start - 0x8000)
+	lui	$4,%hi(_start)
+	addiu	$4,$4,%lo(_start)
+	lui	$4,%hi(_start + 0x7ff0)
+	addiu	$4,$4,%lo(_start + 0x7ff0)
+	lui	$4,%hi(_start + 0x8010)
+	addiu	$4,$4,%lo(_start + 0x8010)
+
+	lui	$4,%got(tstarta - 0x8010)
+	addiu	$4,$4,%lo(tstarta - 0x8010)
+	lui	$4,%got(tstarta - 0x8000)
+	addiu	$4,$4,%lo(tstarta - 0x8000)
+	lui	$4,%got(tstarta)
+	addiu	$4,$4,%lo(tstarta)
+	lui	$4,%got(tstarta + 0x7ff0)
+	addiu	$4,$4,%lo(tstarta + 0x7ff0)
+	lui	$4,%got(tstarta + 0x8010)
+	addiu	$4,$4,%lo(tstarta + 0x8010)
+
+	lui	$4,%got(t32a - 0x8010)
+	addiu	$4,$4,%lo(t32a - 0x8010)
+	lui	$4,%got(t32a - 0x8000)
+	addiu	$4,$4,%lo(t32a - 0x8000)
+	lui	$4,%got(t32a)
+	addiu	$4,$4,%lo(t32a)
+	lui	$4,%got(t32a + 0x7ff0)
+	addiu	$4,$4,%lo(t32a + 0x7ff0)
+	lui	$4,%got(t32a + 0x8010)
+	addiu	$4,$4,%lo(t32a + 0x8010)
+
+	addiu	$4,$4,%gp_rel(sdg - 4)
+	addiu	$4,$4,%gp_rel(sdg)
+	addiu	$4,$4,%gp_rel(sdg + 4)
+
+	addiu	$4,$4,%gp_rel(sdla - 4)
+	addiu	$4,$4,%gp_rel(sdla)
+	addiu	$4,$4,%gp_rel(sdla + 4)
+
+	jal	tstarta - 4
+	nop
+	jal	tstarta
+	nop
+	jal	tstarta + 4
+	nop
+
+	jal	t32a - 4
+	nop
+	jal	t32a
+	nop
+	jal	t32a + 4
+	nop
+
+	jal	_start - 4
+	nop
+	jal	_start
+	nop
+	jal	_start + 4
+	nop
+
+	.org	0xfff0
+
+	.end	tstarta
+
+	.section .sdata
+	.space	16
+sdg:
+sdla:
+	.space	16
diff --git a/ld/testsuite/ld-mips-elf/reloc-1b.s b/ld/testsuite/ld-mips-elf/reloc-1b.s
new file mode 100644
index 0000000..8b9544c
--- /dev/null
+++ b/ld/testsuite/ld-mips-elf/reloc-1b.s
@@ -0,0 +1,95 @@
+	.set	noreorder
+	.ent	tstartb
+tstartb:
+	lui	$4,%hi(tstartb - 0x8010)	# .text + 0x7fe0
+	addiu	$4,$4,%lo(tstartb - 0x8010)
+	lui	$4,%hi(tstartb - 0x8000)	# .text + 0x7ff0
+	addiu	$4,$4,%lo(tstartb - 0x8000)
+	lui	$4,%hi(tstartb)			# .text + 0xfff0
+	addiu	$4,$4,%lo(tstartb)
+	lui	$4,%hi(tstartb + 0x7ff0)	# .text + 0x17fe0
+	addiu	$4,$4,%lo(tstartb + 0x7ff0)
+t32b:
+	lui	$4,%hi(tstartb + 0x8010)	# .text + 0x18000
+	addiu	$4,$4,%lo(tstartb + 0x8010)
+
+	lui	$4,%hi(t32b - 0x8010)		# .text + 0x8000
+	addiu	$4,$4,%lo(t32b - 0x8010)
+	lui	$4,%hi(t32b - 0x8000)		# .text + 0x8010
+	addiu	$4,$4,%lo(t32b - 0x8000)
+	lui	$4,%hi(t32b)			# .text + 0x10010
+	addiu	$4,$4,%lo(t32b)
+	lui	$4,%hi(t32b + 0x7ff0)		# .text + 0x18000
+	addiu	$4,$4,%lo(t32b + 0x7ff0)
+	lui	$4,%hi(t32b + 0x8010)		# .text + 0x18020
+	addiu	$4,$4,%lo(t32b + 0x8010)
+
+	lui	$4,%hi(_start - 0x8010)
+	addiu	$4,$4,%lo(_start - 0x8010)
+	lui	$4,%hi(_start - 0x8000)
+	addiu	$4,$4,%lo(_start - 0x8000)
+	lui	$4,%hi(_start)
+	addiu	$4,$4,%lo(_start)
+	lui	$4,%hi(_start + 0x7ff0)
+	addiu	$4,$4,%lo(_start + 0x7ff0)
+	lui	$4,%hi(_start + 0x8010)
+	addiu	$4,$4,%lo(_start + 0x8010)
+
+	lui	$4,%got(tstartb - 0x8010)	# .text + 0x7fe0
+	addiu	$4,$4,%lo(tstartb - 0x8010)
+	lui	$4,%got(tstartb - 0x8000)	# .text + 0x7ff0
+	addiu	$4,$4,%lo(tstartb - 0x8000)
+	lui	$4,%got(tstartb)			# .text + 0xfff0
+	addiu	$4,$4,%lo(tstartb)
+	lui	$4,%got(tstartb + 0x7ff0)	# .text + 0x17fe0
+	addiu	$4,$4,%lo(tstartb + 0x7ff0)
+	lui	$4,%got(tstartb + 0x8010)	# .text + 0x18000
+	addiu	$4,$4,%lo(tstartb + 0x8010)
+
+	lui	$4,%got(t32b - 0x8010)		# .text + 0x8000
+	addiu	$4,$4,%lo(t32b - 0x8010)
+	lui	$4,%got(t32b - 0x8000)		# .text + 0x8010
+	addiu	$4,$4,%lo(t32b - 0x8000)
+	lui	$4,%got(t32b)			# .text + 0x10010
+	addiu	$4,$4,%lo(t32b)
+	lui	$4,%got(t32b + 0x7ff0)		# .text + 0x18000
+	addiu	$4,$4,%lo(t32b + 0x7ff0)
+	lui	$4,%got(t32b + 0x8010)		# .text + 0x18020
+	addiu	$4,$4,%lo(t32b + 0x8010)
+
+	addiu	$4,$4,%gp_rel(sdg - 4)
+	addiu	$4,$4,%gp_rel(sdg)
+	addiu	$4,$4,%gp_rel(sdg + 4)
+
+	addiu	$4,$4,%gp_rel(sdlb - 4)
+	addiu	$4,$4,%gp_rel(sdlb)
+	addiu	$4,$4,%gp_rel(sdlb + 4)
+
+	jal	tstartb - 4			# .text + 0xffec
+	nop
+	jal	tstartb				# .text + 0xfff0
+	nop
+	jal	tstartb + 4			# .text + 0xfff4
+	nop
+
+	jal	t32b - 4			# .text + 0x1000c
+	nop
+	jal	t32b				# .text + 0x10010
+	nop
+	jal	t32b + 4			# .text + 0x10014
+	nop
+
+	jal	_start - 4
+	nop
+	jal	_start
+	nop
+	jal	_start + 4
+	nop
+
+	.space	16
+	.end	tstartb
+
+	.section .sdata
+	.space	16
+sdlb:
+	.space	16
diff --git a/ld/testsuite/ld-mips-elf/reloc-2.d b/ld/testsuite/ld-mips-elf/reloc-2.d
new file mode 100644
index 0000000..740211e
--- /dev/null
+++ b/ld/testsuite/ld-mips-elf/reloc-2.d
@@ -0,0 +1,169 @@
+#source: reloc-2a.s -EB -mabi=32
+#source: reloc-2b.s -EB -mabi=32
+#ld: --oformat=srec -Treloc-2.ld
+#objdump: -D -mmips:4000 --endian=big
+
+.*:     file format .*
+
+Disassembly of section .*:
+
+.* <.*>:
+#
+# Relocations against tstarta
+#
+.*:	3c040020 	lui	a0,0x20
+.*:	2484fff0 	addiu	a0,a0,-16
+.*:	3c040020 	lui	a0,0x20
+.*:	24840000 	addiu	a0,a0,0
+.*:	3c040021 	lui	a0,0x21
+.*:	24848000 	addiu	a0,a0,-32768
+.*:	3c040021 	lui	a0,0x21
+.*:	2484fff0 	addiu	a0,a0,-16
+.*:	3c040021 	lui	a0,0x21
+.*:	24840010 	addiu	a0,a0,16
+#
+# Relocations against t32a
+#
+.*:	3c040020 	lui	a0,0x20
+.*:	24840010 	addiu	a0,a0,16
+.*:	3c040020 	lui	a0,0x20
+.*:	24840020 	addiu	a0,a0,32
+.*:	3c040021 	lui	a0,0x21
+.*:	24848020 	addiu	a0,a0,-32736
+.*:	3c040021 	lui	a0,0x21
+.*:	24840010 	addiu	a0,a0,16
+.*:	3c040021 	lui	a0,0x21
+.*:	24840030 	addiu	a0,a0,48
+#
+# Relocations against _start
+#
+.*:	3c040020 	lui	a0,0x20
+.*:	2484fff0 	addiu	a0,a0,-16
+.*:	3c040020 	lui	a0,0x20
+.*:	24840000 	addiu	a0,a0,0
+.*:	3c040021 	lui	a0,0x21
+.*:	24848000 	addiu	a0,a0,-32768
+.*:	3c040021 	lui	a0,0x21
+.*:	2484fff0 	addiu	a0,a0,-16
+.*:	3c040021 	lui	a0,0x21
+.*:	24840010 	addiu	a0,a0,16
+#
+# Relocations against sdg
+#
+.*:	2484edd8 	addiu	a0,a0,-4648
+.*:	2484eddc 	addiu	a0,a0,-4644
+.*:	2484ede0 	addiu	a0,a0,-4640
+#
+# Relocations against sdla
+#
+.*:	2484edd8 	addiu	a0,a0,-4648
+.*:	2484eddc 	addiu	a0,a0,-4644
+.*:	2484ede0 	addiu	a0,a0,-4640
+#
+# Relocations against tstarta
+#
+.*:	0c081fff 	jal	0x207ffc
+.*:	00000000 	nop
+.*:	0c082000 	jal	0x208000
+.*:	00000000 	nop
+.*:	0c082001 	jal	0x208004
+.*:	00000000 	nop
+#
+# Relocations against t32a
+#
+.*:	0c082007 	jal	0x20801c
+.*:	00000000 	nop
+.*:	0c082008 	jal	0x208020
+.*:	00000000 	nop
+.*:	0c082009 	jal	0x208024
+.*:	00000000 	nop
+#
+# Relocations against _start
+#
+.*:	0c081fff 	jal	0x207ffc
+.*:	00000000 	nop
+.*:	0c082000 	jal	0x208000
+.*:	00000000 	nop
+.*:	0c082001 	jal	0x208004
+.*:	00000000 	nop
+	\.\.\.
+#
+# Relocations against tstartb
+#
+.*:	3c040021 	lui	a0,0x21
+.*:	2484ffe0 	addiu	a0,a0,-32
+.*:	3c040021 	lui	a0,0x21
+.*:	2484fff0 	addiu	a0,a0,-16
+.*:	3c040021 	lui	a0,0x21
+.*:	24847ff0 	addiu	a0,a0,32752
+.*:	3c040022 	lui	a0,0x22
+.*:	2484ffe0 	addiu	a0,a0,-32
+.*:	3c040022 	lui	a0,0x22
+.*:	24840000 	addiu	a0,a0,0
+#
+# Relocations against t32b
+#
+.*:	3c040021 	lui	a0,0x21
+.*:	24840000 	addiu	a0,a0,0
+.*:	3c040021 	lui	a0,0x21
+.*:	24840010 	addiu	a0,a0,16
+.*:	3c040022 	lui	a0,0x22
+.*:	24848010 	addiu	a0,a0,-32752
+.*:	3c040022 	lui	a0,0x22
+.*:	24840000 	addiu	a0,a0,0
+.*:	3c040022 	lui	a0,0x22
+.*:	24840020 	addiu	a0,a0,32
+#
+# Relocations against _start
+#
+.*:	3c040020 	lui	a0,0x20
+.*:	2484fff0 	addiu	a0,a0,-16
+.*:	3c040020 	lui	a0,0x20
+.*:	24840000 	addiu	a0,a0,0
+.*:	3c040021 	lui	a0,0x21
+.*:	24848000 	addiu	a0,a0,-32768
+.*:	3c040021 	lui	a0,0x21
+.*:	2484fff0 	addiu	a0,a0,-16
+.*:	3c040021 	lui	a0,0x21
+.*:	24840010 	addiu	a0,a0,16
+#
+# Relocations against sdg
+#
+.*:	2484edd8 	addiu	a0,a0,-4648
+.*:	2484eddc 	addiu	a0,a0,-4644
+.*:	2484ede0 	addiu	a0,a0,-4640
+#
+# Relocations against sdl2
+#
+.*:	2484edf8 	addiu	a0,a0,-4616
+.*:	2484edfc 	addiu	a0,a0,-4612
+.*:	2484ee00 	addiu	a0,a0,-4608
+#
+# Relocations against tstartb
+#
+.*:	0c085ffb 	jal	0x217fec
+.*:	00000000 	nop
+.*:	0c085ffc 	jal	0x217ff0
+.*:	00000000 	nop
+.*:	0c085ffd 	jal	0x217ff4
+.*:	00000000 	nop
+#
+# Relocations against t32b
+#
+.*:	0c086003 	jal	0x21800c
+.*:	00000000 	nop
+.*:	0c086004 	jal	0x218010
+.*:	00000000 	nop
+.*:	0c086005 	jal	0x218014
+.*:	00000000 	nop
+#
+# Relocations against _start
+#
+.*:	0c081fff 	jal	0x207ffc
+.*:	00000000 	nop
+.*:	0c082000 	jal	0x208000
+.*:	00000000 	nop
+.*:	0c082001 	jal	0x208004
+.*:	00000000 	nop
+	\.\.\.
+#pass
diff --git a/ld/testsuite/ld-mips-elf/reloc-2.ld b/ld/testsuite/ld-mips-elf/reloc-2.ld
new file mode 100644
index 0000000..ff0b291
--- /dev/null
+++ b/ld/testsuite/ld-mips-elf/reloc-2.ld
@@ -0,0 +1,9 @@
+SECTIONS
+{
+  . = 0x208000;
+  .text : { *(.text) }
+  . = 0x400000;
+  _gp = 0x401234;
+  .sdata : { *(.sdata) }
+  /DISCARD/ : { *(*) }
+}
diff --git a/ld/testsuite/ld-mips-elf/reloc-2a.s b/ld/testsuite/ld-mips-elf/reloc-2a.s
new file mode 100644
index 0000000..0ea830a
--- /dev/null
+++ b/ld/testsuite/ld-mips-elf/reloc-2a.s
@@ -0,0 +1,78 @@
+	.globl	_start
+	.globl	sdg
+	.set	noreorder
+	.ent	tstarta
+tstarta:
+_start:
+	lui	$4,%hi(tstarta - 0x8010)
+	addiu	$4,$4,%lo(tstarta - 0x8010)
+	lui	$4,%hi(tstarta - 0x8000)
+	addiu	$4,$4,%lo(tstarta - 0x8000)
+	lui	$4,%hi(tstarta)
+	addiu	$4,$4,%lo(tstarta)
+	lui	$4,%hi(tstarta + 0x7ff0)
+	addiu	$4,$4,%lo(tstarta + 0x7ff0)
+t32a:
+	lui	$4,%hi(tstarta + 0x8010)
+	addiu	$4,$4,%lo(tstarta + 0x8010)
+
+	lui	$4,%hi(t32a - 0x8010)
+	addiu	$4,$4,%lo(t32a - 0x8010)
+	lui	$4,%hi(t32a - 0x8000)
+	addiu	$4,$4,%lo(t32a - 0x8000)
+	lui	$4,%hi(t32a)
+	addiu	$4,$4,%lo(t32a)
+	lui	$4,%hi(t32a + 0x7ff0)
+	addiu	$4,$4,%lo(t32a + 0x7ff0)
+	lui	$4,%hi(t32a + 0x8010)
+	addiu	$4,$4,%lo(t32a + 0x8010)
+
+	lui	$4,%hi(_start - 0x8010)
+	addiu	$4,$4,%lo(_start - 0x8010)
+	lui	$4,%hi(_start - 0x8000)
+	addiu	$4,$4,%lo(_start - 0x8000)
+	lui	$4,%hi(_start)
+	addiu	$4,$4,%lo(_start)
+	lui	$4,%hi(_start + 0x7ff0)
+	addiu	$4,$4,%lo(_start + 0x7ff0)
+	lui	$4,%hi(_start + 0x8010)
+	addiu	$4,$4,%lo(_start + 0x8010)
+
+	addiu	$4,$4,%gp_rel(sdg - 4)
+	addiu	$4,$4,%gp_rel(sdg)
+	addiu	$4,$4,%gp_rel(sdg + 4)
+
+	addiu	$4,$4,%gp_rel(sdla - 4)
+	addiu	$4,$4,%gp_rel(sdla)
+	addiu	$4,$4,%gp_rel(sdla + 4)
+
+	jal	tstarta - 4
+	nop
+	jal	tstarta
+	nop
+	jal	tstarta + 4
+	nop
+
+	jal	t32a - 4
+	nop
+	jal	t32a
+	nop
+	jal	t32a + 4
+	nop
+
+	jal	_start - 4
+	nop
+	jal	_start
+	nop
+	jal	_start + 4
+	nop
+
+	.org	0xfff0
+
+	.end	tstarta
+
+	.section .sdata
+	.space	16
+sdg:
+sdla:
+	.space	16
diff --git a/ld/testsuite/ld-mips-elf/reloc-2b.s b/ld/testsuite/ld-mips-elf/reloc-2b.s
new file mode 100644
index 0000000..3a9d694
--- /dev/null
+++ b/ld/testsuite/ld-mips-elf/reloc-2b.s
@@ -0,0 +1,73 @@
+	.set	noreorder
+	.ent	tstartb
+tstartb:
+	lui	$4,%hi(tstartb - 0x8010)	# .text + 0x7fe0
+	addiu	$4,$4,%lo(tstartb - 0x8010)
+	lui	$4,%hi(tstartb - 0x8000)	# .text + 0x7ff0
+	addiu	$4,$4,%lo(tstartb - 0x8000)
+	lui	$4,%hi(tstartb)			# .text + 0xfff0
+	addiu	$4,$4,%lo(tstartb)
+	lui	$4,%hi(tstartb + 0x7ff0)	# .text + 0x17fe0
+	addiu	$4,$4,%lo(tstartb + 0x7ff0)
+t32b:
+	lui	$4,%hi(tstartb + 0x8010)	# .text + 0x18000
+	addiu	$4,$4,%lo(tstartb + 0x8010)
+
+	lui	$4,%hi(t32b - 0x8010)		# .text + 0x8000
+	addiu	$4,$4,%lo(t32b - 0x8010)
+	lui	$4,%hi(t32b - 0x8000)		# .text + 0x8010
+	addiu	$4,$4,%lo(t32b - 0x8000)
+	lui	$4,%hi(t32b)			# .text + 0x10010
+	addiu	$4,$4,%lo(t32b)
+	lui	$4,%hi(t32b + 0x7ff0)		# .text + 0x18000
+	addiu	$4,$4,%lo(t32b + 0x7ff0)
+	lui	$4,%hi(t32b + 0x8010)		# .text + 0x18020
+	addiu	$4,$4,%lo(t32b + 0x8010)
+
+	lui	$4,%hi(_start - 0x8010)
+	addiu	$4,$4,%lo(_start - 0x8010)
+	lui	$4,%hi(_start - 0x8000)
+	addiu	$4,$4,%lo(_start - 0x8000)
+	lui	$4,%hi(_start)
+	addiu	$4,$4,%lo(_start)
+	lui	$4,%hi(_start + 0x7ff0)
+	addiu	$4,$4,%lo(_start + 0x7ff0)
+	lui	$4,%hi(_start + 0x8010)
+	addiu	$4,$4,%lo(_start + 0x8010)
+
+	addiu	$4,$4,%gp_rel(sdg - 4)
+	addiu	$4,$4,%gp_rel(sdg)
+	addiu	$4,$4,%gp_rel(sdg + 4)
+
+	addiu	$4,$4,%gp_rel(sdlb - 4)
+	addiu	$4,$4,%gp_rel(sdlb)
+	addiu	$4,$4,%gp_rel(sdlb + 4)
+
+	jal	tstartb - 4			# .text + 0xffec
+	nop
+	jal	tstartb				# .text + 0xfff0
+	nop
+	jal	tstartb + 4			# .text + 0xfff4
+	nop
+
+	jal	t32b - 4			# .text + 0x1000c
+	nop
+	jal	t32b				# .text + 0x10010
+	nop
+	jal	t32b + 4			# .text + 0x10014
+	nop
+
+	jal	_start - 4
+	nop
+	jal	_start
+	nop
+	jal	_start + 4
+	nop
+
+	.space	16
+	.end	tstartb
+
+	.section .sdata
+	.space	16
+sdlb:
+	.space	16
diff --git a/ld/testsuite/ld-mips-elf/reloc-3-r.d b/ld/testsuite/ld-mips-elf/reloc-3-r.d
new file mode 100644
index 0000000..9624e6e
--- /dev/null
+++ b/ld/testsuite/ld-mips-elf/reloc-3-r.d
@@ -0,0 +1,83 @@
+#source: reloc-3a.s -mabi=32 -membedded-pic
+#source: reloc-3b.s -mabi=32 -membedded-pic
+#ld: -r
+#objdump: -dr
+
+.*:     file format .*
+
+Disassembly of section \.text:
+
+.* <.*>:
+#
+# Relocations against lda
+#
+.*:	3c04ffff 	lui	a0,0xffff
+			.*: R_MIPS_GNU_REL_HI16	\.text2
+.*:	24847ffc 	addiu	a0,a0,32764
+			.*: R_MIPS_GNU_REL_LO16	\.text2
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_GNU_REL_HI16	\.text2
+.*:	24848014 	addiu	a0,a0,-32748
+			.*: R_MIPS_GNU_REL_LO16	\.text2
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_GNU_REL_HI16	\.text2
+.*:	2484001c 	addiu	a0,a0,28
+			.*: R_MIPS_GNU_REL_LO16	\.text2
+.*:	3c040001 	lui	a0,0x1
+			.*: R_MIPS_GNU_REL_HI16	\.text2
+.*:	24848014 	addiu	a0,a0,-32748
+			.*: R_MIPS_GNU_REL_LO16	\.text2
+.*:	3c040001 	lui	a0,0x1
+			.*: R_MIPS_GNU_REL_HI16	\.text2
+.*:	2484803c 	addiu	a0,a0,-32708
+			.*: R_MIPS_GNU_REL_LO16	\.text2
+	\.\.\.
+
+.* <.*>:
+#
+# Relocations against gd
+#
+.*:	3c04ffff 	lui	a0,0xffff
+			.*: R_MIPS_GNU_REL_HI16	gd
+.*:	24847ff4 	addiu	a0,a0,32756
+			.*: R_MIPS_GNU_REL_LO16	gd
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_GNU_REL_HI16	gd
+.*:	2484800c 	addiu	a0,a0,-32756
+			.*: R_MIPS_GNU_REL_LO16	gd
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_GNU_REL_HI16	gd
+.*:	24840014 	addiu	a0,a0,20
+			.*: R_MIPS_GNU_REL_LO16	gd
+.*:	3c040001 	lui	a0,0x1
+			.*: R_MIPS_GNU_REL_HI16	gd
+.*:	2484800c 	addiu	a0,a0,-32756
+			.*: R_MIPS_GNU_REL_LO16	gd
+.*:	3c040001 	lui	a0,0x1
+			.*: R_MIPS_GNU_REL_HI16	gd
+.*:	24848034 	addiu	a0,a0,-32716
+			.*: R_MIPS_GNU_REL_LO16	gd
+#
+# Relocations against ldb
+#
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_GNU_REL_HI16	\.text2
+.*:	2484802c 	addiu	a0,a0,-32724
+			.*: R_MIPS_GNU_REL_LO16	\.text2
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_GNU_REL_HI16	\.text2
+.*:	24848044 	addiu	a0,a0,-32700
+			.*: R_MIPS_GNU_REL_LO16	\.text2
+.*:	3c040000 	lui	a0,0x0
+			.*: R_MIPS_GNU_REL_HI16	\.text2
+.*:	2484004c 	addiu	a0,a0,76
+			.*: R_MIPS_GNU_REL_LO16	\.text2
+.*:	3c040001 	lui	a0,0x1
+			.*: R_MIPS_GNU_REL_HI16	\.text2
+.*:	24848044 	addiu	a0,a0,-32700
+			.*: R_MIPS_GNU_REL_LO16	\.text2
+.*:	3c040001 	lui	a0,0x1
+			.*: R_MIPS_GNU_REL_HI16	\.text2
+.*:	2484806c 	addiu	a0,a0,-32660
+			.*: R_MIPS_GNU_REL_LO16	\.text2
+	\.\.\.
diff --git a/ld/testsuite/ld-mips-elf/reloc-3-srec.d b/ld/testsuite/ld-mips-elf/reloc-3-srec.d
new file mode 100644
index 0000000..a4a7d24
--- /dev/null
+++ b/ld/testsuite/ld-mips-elf/reloc-3-srec.d
@@ -0,0 +1,54 @@
+#source: reloc-3a.s -mabi=32 -membedded-pic -EB
+#source: reloc-3b.s -mabi=32 -membedded-pic -EB
+#ld: --oformat=srec -Treloc-3.ld
+#objdump: -D -mmips:4000 --endian=big
+
+.*:     file format .*
+
+Disassembly of section .*:
+
+.* <.*>:
+# .text2 - tstarta = 0x108000
+# .text2 - tstartb = 0x098010
+#
+# Relocations against lda
+#
+.*:	3c040010 	lui	a0,0x10
+.*:	2484fff8 	addiu	a0,a0,-8
+.*:	3c040010 	lui	a0,0x10
+.*:	24840008 	addiu	a0,a0,8
+.*:	3c040011 	lui	a0,0x11
+.*:	24848008 	addiu	a0,a0,-32760
+.*:	3c040011 	lui	a0,0x11
+.*:	2484fff8 	addiu	a0,a0,-8
+.*:	3c040011 	lui	a0,0x11
+.*:	24840018 	addiu	a0,a0,24
+	\.\.\.
+#
+# Relocations against gd
+#
+.*:	3c04000f 	lui	a0,0xf
+.*:	24840004 	addiu	a0,a0,4
+.*:	3c04000f 	lui	a0,0xf
+.*:	24840014 	addiu	a0,a0,20
+.*:	3c040010 	lui	a0,0x10
+.*:	24848014 	addiu	a0,a0,-32748
+.*:	3c040010 	lui	a0,0x10
+.*:	24840004 	addiu	a0,a0,4
+.*:	3c040010 	lui	a0,0x10
+.*:	24840024 	addiu	a0,a0,36
+#
+# Relocations against ldb
+#
+.*:	3c04000f 	lui	a0,0xf
+.*:	24840010 	addiu	a0,a0,16
+.*:	3c04000f 	lui	a0,0xf
+.*:	24840020 	addiu	a0,a0,32
+.*:	3c040010 	lui	a0,0x10
+.*:	24848020 	addiu	a0,a0,-32736
+.*:	3c040010 	lui	a0,0x10
+.*:	24840010 	addiu	a0,a0,16
+.*:	3c040010 	lui	a0,0x10
+.*:	24840030 	addiu	a0,a0,48
+	\.\.\.
+#pass
diff --git a/ld/testsuite/ld-mips-elf/reloc-3.ld b/ld/testsuite/ld-mips-elf/reloc-3.ld
new file mode 100644
index 0000000..a918bf9
--- /dev/null
+++ b/ld/testsuite/ld-mips-elf/reloc-3.ld
@@ -0,0 +1,8 @@
+SECTIONS
+{
+  . = 0x208000;
+  .text : { *(.text) }
+  . = 0x310000;
+  .text2 : { *(.text2) }
+  /DISCARD/ : { *(*) }
+}
diff --git a/ld/testsuite/ld-mips-elf/reloc-3a.s b/ld/testsuite/ld-mips-elf/reloc-3a.s
new file mode 100644
index 0000000..f0cdabd
--- /dev/null
+++ b/ld/testsuite/ld-mips-elf/reloc-3a.s
@@ -0,0 +1,38 @@
+	.globl	_start
+	.globl	gd
+	.ent	tstarta
+tstarta:
+_start:
+	la	$4,lda-tstarta-0x8010
+			# (.text2+8-0x8010) - tstarta [+ (tstarta+0x4)]
+			#     relocation:  .text2 - 0x8004
+			#     final value: .text2 - tstarta - 0x8008
+
+	la	$4,lda-tstarta-0x8000
+			# (.text2+8-0x8000) - tstarta [+ (tstarta+0xc)]
+			#     relocation:  .text2 - 0x7fec
+			#     final value: .text2 - tstarta - 0x7ff8
+
+	la	$4,lda-tstarta
+			# (.text2+8) - tstarta [+ (tstarta+0x14)]
+			#     relocation:  .text2 + 0x1c
+			#     final value: .text2 - tstarta + 0x8
+
+	la	$4,lda-tstarta+0x7ff0
+			# (.text2+8+0x7ff0) - tstarta [+ (tstarta+0x1c)]
+			#     relocation:  .text2 + 0x8014
+			#     final value: .text2 - tstarta + 0x7ff8
+
+	la	$4,lda-tstarta+0x8010	# (.text2+8)-(tstarta+0x8010)+0x24
+			# (.text2+8+0x8010) - tstarta [+ (tstarta+0x24)]
+			#     relocation:  .text2 + 0x803c
+			#     final value: .text2 - tstarta + 0x8018
+
+	.end	tstarta
+
+	.org	0xfff0
+	.section .text2
+	.word	1
+gd:	.word	2
+lda:	.word	3
+	.word	4
diff --git a/ld/testsuite/ld-mips-elf/reloc-3b.s b/ld/testsuite/ld-mips-elf/reloc-3b.s
new file mode 100644
index 0000000..8d50334
--- /dev/null
+++ b/ld/testsuite/ld-mips-elf/reloc-3b.s
@@ -0,0 +1,58 @@
+	.globl	_start
+	.globl	gd
+	.ent	tstartb
+tstartb:
+	la	$4,gd-tstartb-0x8010
+			# (gd-0x8010) - tstartb [+ (tstartb+0x4)]
+			#     relocation:  gd - 0x800c
+			#     final value: gd - tstartb - 0x8010
+
+	la	$4,gd-tstartb-0x8000
+			# (gd-0x8000) - tstartb [+ (tstartb+0xc)]
+			#     relocation:  gd - 0x7ff4
+			#     final value: gd - tstartb - 0x8000
+
+	la	$4,gd-tstartb
+			# (gd) - tstartb [+ (tstartb+0x14)]
+			#     relocation:  gd + 0x14
+			#     final value: gd - tstartb
+
+	la	$4,gd-tstartb+0x7ff0
+			# (gd+0x7ff0) - tstartb [+ (tstartb+0x1c)]
+			#     relocation:  gd + 0x800c
+			#     final value: gd - tstartb + 0x7ff0
+
+	la	$4,gd-tstartb+0x8010
+			# (gd+0x8010) - tstartb [+ (tstartb+0x24)]
+			#     relocation:  gd + 0x8034
+			#     final value: gd - tstartb + 0x8010
+
+	la	$4,ldb-tstartb-0x8010
+			# (.text2+0x10-0x8010) - tstartb [+ (tstartb+0x2c)]
+			#     relocation:  .text2 - 0x7fd4
+			#     final value: .text2 - tstartb - 0x8000
+
+	la	$4,ldb-tstartb-0x8000
+			# (.text2+0x10-0x8000) - tstartb [+ (tstartb+0x34)]
+			#     relocation:  .text2 - 0x7fbc
+			#     final value: .text2 - tstartb - 0x7ff0
+
+	la	$4,ldb-tstartb
+			# (.text2+0x10) - tstartb [+ (tstartb+0x3c)]
+			#     relocation:  .text2 + 0x4c
+			#     final value: .text2 - tstartb + 0x10
+
+	la	$4,ldb-tstartb+0x7ff0
+			# (.text2+0x10+0x7ff0) - tstartb [+ (tstartb+0x44)]
+			#     relocation:  .text2 + 0x8044
+			#     final value: .text2 - tstartb + 0x8000
+
+	la	$4,ldb-tstartb+0x8010
+			# (.text2+0x10+0x8010) - tstartb [+ (tstartb+0x4c)]
+			#     relocation:  .text2 + 0x806c
+			#     final value: .text2 - tstartb + 0x8020
+
+	.end	tstartb
+	.space	16
+	.section .text2
+ldb:	.word	5