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| author | Maciej W. Rozycki <macro@imgtec.com> | 2016-12-23 17:05:01 +0000 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@imgtec.com> | 2016-12-23 19:37:13 +0000 |
| commit | d8722d7641d234dcd3d1f2254fbc5d9cf234e4e6 (patch) | |
| tree | 14e776f31302da5b1f23383fd025d6db926bede6 /include | |
| parent | 0674ee5dada21c8deec690ca66d5b2870f13ea49 (diff) | |
| download | fsf-binutils-gdb-d8722d7641d234dcd3d1f2254fbc5d9cf234e4e6.zip fsf-binutils-gdb-d8722d7641d234dcd3d1f2254fbc5d9cf234e4e6.tar.gz fsf-binutils-gdb-d8722d7641d234dcd3d1f2254fbc5d9cf234e4e6.tar.bz2 | |
MIPS16: Reassign `0' and `4' operand codes
Replace `0' and `4' operand codes with `.' and `F' respectively to free
up the `0'-`4' consecutive range. No functional change.
gas/
* config/tc-mips.c (mips16_macro_build): Replace `0' and `4'
operand codes with `.' and `F' respectively.
(mips16_macro): Likewise.
include/
* opcode/mips.h: Replace `0' and `4' operand codes with `.' and
`F' respectively.
opcodes/
* mips16-opc.c (decode_mips16_operand): Replace `0' and `4'
operand codes with `.' and `F' respectively.
(mips16_opcodes): Likewise.
Diffstat (limited to 'include')
| -rw-r--r-- | include/ChangeLog | 5 | ||||
| -rw-r--r-- | include/opcode/mips.h | 10 |
2 files changed, 10 insertions, 5 deletions
diff --git a/include/ChangeLog b/include/ChangeLog index f771bd1..04c02ce 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,5 +1,10 @@ 2016-12-23 Maciej W. Rozycki <macro@imgtec.com> + * opcode/mips.h: Replace `0' and `4' operand codes with `.' and + `F' respectively. + +2016-12-23 Maciej W. Rozycki <macro@imgtec.com> + * opcode/mips.h (INSN2_SHORT_ONLY): New macro. 2016-12-21 Alan Modra <amodra@gmail.com> diff --git a/include/opcode/mips.h b/include/opcode/mips.h index cf661c8..e00f682 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -1803,7 +1803,7 @@ extern int bfd_mips_num_opcodes; "Z" 3 bit register (MIPS16OP_*_MOVE32Z) "v" 3 bit same register as source and destination (MIPS16OP_*_RX) "w" 3 bit same register as source and destination (MIPS16OP_*_RY) - "0" zero register ($0) + "." zero register ($0) "S" stack pointer ($sp or $29) "P" program counter "R" return address register ($ra or $31) @@ -1823,8 +1823,8 @@ extern int bfd_mips_num_opcodes; "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned) "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned) "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned) - "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed) "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5) + "F" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed) "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5) "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5) "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5) @@ -1844,9 +1844,9 @@ extern int bfd_mips_num_opcodes; "M" 7 bit register list for restore instruction (18 bit extended) Characters used so far, for quick reference when adding more: - " 456 8 0" - "[]<" - "ABCDE HI KLM P RS UVWXYZ" + " 56 8 " + ".[]<" + "ABCDEF HI KLM P RS UVWXYZ" "a e ijklm pq vwxyz" */ |