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| author | Maciej W. Rozycki <macro@imgtec.com> | 2016-12-07 02:27:57 +0000 |
|---|---|---|
| committer | Maciej W. Rozycki <macro@imgtec.com> | 2016-12-07 12:26:11 +0000 |
| commit | b8760d2cb51517789110c7b2dbd8f61dce08291d (patch) | |
| tree | b1a8992f85385f8f9a512db81154546529ccb04f /include | |
| parent | be0fcbee1d47558af13288c6aece922dd4be6df5 (diff) | |
| download | fsf-binutils-gdb-b8760d2cb51517789110c7b2dbd8f61dce08291d.zip fsf-binutils-gdb-b8760d2cb51517789110c7b2dbd8f61dce08291d.tar.gz fsf-binutils-gdb-b8760d2cb51517789110c7b2dbd8f61dce08291d.tar.bz2 | |
MIPS/include: opcode/mips.h: Add a comment for ASE_DSPR3
Complement commit 8f4f9071ad5f ("Add MIPS32 DSPr3 support.").
include/
* opcode/mips.h (ASE_DSPR3): Add a comment.
Diffstat (limited to 'include')
| -rw-r--r-- | include/ChangeLog | 4 | ||||
| -rw-r--r-- | include/opcode/mips.h | 1 |
2 files changed, 5 insertions, 0 deletions
diff --git a/include/ChangeLog b/include/ChangeLog index bb748fe..7d37b15 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,7 @@ +2016-12-07 Maciej W. Rozycki <macro@imgtec.com> + + * opcode/mips.h (ASE_DSPR3): Add a comment. + 2016-12-05 Szabolcs Nagy <szabolcs.nagy@arm.com> * opcode/arm.h (ARM_EXT2_V8_3A, ARM_AEXT2_V8_3A): New. diff --git a/include/opcode/mips.h b/include/opcode/mips.h index b1d4ef6..08bc24f 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -1260,6 +1260,7 @@ static const unsigned int mips_isa_table[] = { #define ASE_MSA64 0x00001000 /* eXtended Physical Address (XPA) Extension. */ #define ASE_XPA 0x00002000 +/* DSP R3 Module. */ #define ASE_DSPR3 0x00004000 /* MIPS ISA defines, use instead of hardcoding ISA level. */ |