PowerPC -Mraw disassembly

This adds -Mraw for PowerPC objdump, a disassembler option to display
the underlying machine instruction rather than aliases.  For example,
"rlwinm" always rather than "rotlwi" when the instruction is
performing a simple rotate.

binutils/
	* doc/binutils.texi (objdump): Document PowerPC -M options.
gas/
	* config/tc-ppc.c (md_parse_option): Reject -mraw.
include/
	* opcode/ppc.h (PPC_OPCODE_RAW): Define.
	(PPC_OPCODE_*): Make them all unsigned long long constants.
opcodes/
	* ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags.  Add
	"raw" option.
	(lookup_powerpc): Don't special case -1 dialect.  Handle
	PPC_OPCODE_RAW.
	(print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
	lookup_powerpc call, pass it on second.

2 files changed, 48 insertions, 37 deletions

diff --git a/include/ChangeLog b/include/ChangeLog
index daaad17..7695774 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,8 @@
+2017-03-29  Alan Modra  <amodra@gmail.com>
+
+	* opcode/ppc.h (PPC_OPCODE_RAW): Define.
+	(PPC_OPCODE_*): Make them all unsigned long long constants.
+
 2017-03-27  Pip Cet  <pipcet@gmail.com>
 
 	* elf/wasm32.h: New file to support wasm32 architecture.
diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h
index 34cf27e..c4de834 100644
--- a/include/opcode/ppc.h
+++ b/include/opcode/ppc.h
@@ -74,107 +74,107 @@ extern const int vle_num_opcodes;
 /* Values defined for the flags field of a struct powerpc_opcode.  */
 
 /* Opcode is defined for the PowerPC architecture.  */
-#define PPC_OPCODE_PPC			 1
+#define PPC_OPCODE_PPC		       0x1ull
 
 /* Opcode is defined for the POWER (RS/6000) architecture.  */
-#define PPC_OPCODE_POWER		 2
+#define PPC_OPCODE_POWER	       0x2ull
 
 /* Opcode is defined for the POWER2 (Rios 2) architecture.  */
-#define PPC_OPCODE_POWER2		 4
+#define PPC_OPCODE_POWER2	       0x4ull
 
 /* Opcode is supported by the Motorola PowerPC 601 processor.  The 601
    is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
    but it also supports many additional POWER instructions.  */
-#define PPC_OPCODE_601			 8
+#define PPC_OPCODE_601		       0x8ull
 
 /* Opcode is supported in both the Power and PowerPC architectures
    (ie, compiler's -mcpu=common or assembler's -mcom).  More than just
    the intersection of PPC_OPCODE_PPC with the union of PPC_OPCODE_POWER
    and PPC_OPCODE_POWER2 because many instructions changed mnemonics
    between POWER and POWERPC.  */
-#define PPC_OPCODE_COMMON	      0x10
+#define PPC_OPCODE_COMMON	      0x10ull
 
 /* Opcode is supported for any Power or PowerPC platform (this is
    for the assembler's -many option, and it eliminates duplicates).  */
-#define PPC_OPCODE_ANY		      0x20
+#define PPC_OPCODE_ANY		      0x20ull
 
 /* Opcode is only defined on 64 bit architectures.  */
-#define PPC_OPCODE_64		      0x40
+#define PPC_OPCODE_64		      0x40ull
 
 /* Opcode is supported as part of the 64-bit bridge.  */
-#define PPC_OPCODE_64_BRIDGE	      0x80
+#define PPC_OPCODE_64_BRIDGE	      0x80ull
 
 /* Opcode is supported by Altivec Vector Unit */
-#define PPC_OPCODE_ALTIVEC	     0x100
+#define PPC_OPCODE_ALTIVEC	     0x100ull
 
 /* Opcode is supported by PowerPC 403 processor.  */
-#define PPC_OPCODE_403		     0x200
+#define PPC_OPCODE_403		     0x200ull
 
 /* Opcode is supported by PowerPC BookE processor.  */
-#define PPC_OPCODE_BOOKE	     0x400
+#define PPC_OPCODE_BOOKE	     0x400ull
 
 /* Opcode is supported by PowerPC 440 processor.  */
-#define PPC_OPCODE_440		     0x800
+#define PPC_OPCODE_440		     0x800ull
 
 /* Opcode is only supported by Power4 architecture.  */
-#define PPC_OPCODE_POWER4	    0x1000
+#define PPC_OPCODE_POWER4	    0x1000ull
 
 /* Opcode is only supported by Power7 architecture.  */
-#define PPC_OPCODE_POWER7	    0x2000
+#define PPC_OPCODE_POWER7	    0x2000ull
 
 /* Opcode is only supported by e500x2 Core.  */
-#define PPC_OPCODE_SPE		    0x4000
+#define PPC_OPCODE_SPE		    0x4000ull
 
 /* Opcode is supported by e500x2 Integer select APU.  */
-#define PPC_OPCODE_ISEL		    0x8000
+#define PPC_OPCODE_ISEL		    0x8000ull
 
 /* Opcode is an e500 SPE floating point instruction.  */
-#define PPC_OPCODE_EFS		   0x10000
+#define PPC_OPCODE_EFS		   0x10000ull
 
 /* Opcode is supported by branch locking APU.  */
-#define PPC_OPCODE_BRLOCK	   0x20000
+#define PPC_OPCODE_BRLOCK	   0x20000ull
 
 /* Opcode is supported by performance monitor APU.  */
-#define PPC_OPCODE_PMR		   0x40000
+#define PPC_OPCODE_PMR		   0x40000ull
 
 /* Opcode is supported by cache locking APU.  */
-#define PPC_OPCODE_CACHELCK	   0x80000
+#define PPC_OPCODE_CACHELCK	   0x80000ull
 
 /* Opcode is supported by machine check APU.  */
-#define PPC_OPCODE_RFMCI	  0x100000
+#define PPC_OPCODE_RFMCI	  0x100000ull
 
 /* Opcode is only supported by Power5 architecture.  */
-#define PPC_OPCODE_POWER5	  0x200000
+#define PPC_OPCODE_POWER5	  0x200000ull
 
 /* Opcode is supported by PowerPC e300 family.  */
-#define PPC_OPCODE_E300           0x400000
+#define PPC_OPCODE_E300           0x400000ull
 
 /* Opcode is only supported by Power6 architecture.  */
-#define PPC_OPCODE_POWER6	  0x800000
+#define PPC_OPCODE_POWER6	  0x800000ull
 
 /* Opcode is only supported by PowerPC Cell family.  */
-#define PPC_OPCODE_CELL		 0x1000000
+#define PPC_OPCODE_CELL		 0x1000000ull
 
 /* Opcode is supported by CPUs with paired singles support.  */
-#define PPC_OPCODE_PPCPS	 0x2000000
+#define PPC_OPCODE_PPCPS	 0x2000000ull
 
 /* Opcode is supported by Power E500MC */
-#define PPC_OPCODE_E500MC        0x4000000
+#define PPC_OPCODE_E500MC        0x4000000ull
 
 /* Opcode is supported by PowerPC 405 processor.  */
-#define PPC_OPCODE_405		 0x8000000
+#define PPC_OPCODE_405		 0x8000000ull
 
 /* Opcode is supported by Vector-Scalar (VSX) Unit */
-#define PPC_OPCODE_VSX		0x10000000
+#define PPC_OPCODE_VSX		0x10000000ull
 
 /* Opcode is supported by A2.  */
-#define PPC_OPCODE_A2	 	0x20000000
+#define PPC_OPCODE_A2	 	0x20000000ull
 
 /* Opcode is supported by PowerPC 476 processor.  */
-#define PPC_OPCODE_476		0x40000000
+#define PPC_OPCODE_476		0x40000000ull
 
 /* Opcode is supported by AppliedMicro Titan core */
-#define PPC_OPCODE_TITAN        0x80000000
+#define PPC_OPCODE_TITAN        0x80000000ull
 
 /* Opcode which is supported by the e500 family */
 #define PPC_OPCODE_E500	       0x100000000ull
@@ -206,16 +206,22 @@ extern const int vle_num_opcodes;
 #define PPC_OPCODE_7450	      0x8000000000ull
 
 /* Opcode is supported by ppc821/850/860.  */
-#define PPC_OPCODE_860	      0x10000000000ull
+#define PPC_OPCODE_860	     0x10000000000ull
 
 /* Opcode is only supported by Power9 architecture.  */
-#define PPC_OPCODE_POWER9     0x20000000000ull
+#define PPC_OPCODE_POWER9    0x20000000000ull
 
 /* Opcode is supported by Vector-Scalar (VSX) Unit from ISA 2.08.  */
-#define PPC_OPCODE_VSX3       0x40000000000ull
+#define PPC_OPCODE_VSX3      0x40000000000ull
 
-  /* Opcode is supported by e200z4.  */
-#define PPC_OPCODE_E200Z4     0x80000000000ull
+/* Opcode is supported by e200z4.  */
+#define PPC_OPCODE_E200Z4    0x80000000000ull
+
+/* Disassemble to instructions matching later in the opcode table
+   with fewer "mask" bits set rather than the earlist match.  Fewer
+   "mask" bits set imply a more general form of the opcode, in fact
+   the underlying machine instruction.  */
+#define PPC_OPCODE_RAW	    0x100000000000ull
 
 /* A macro to extract the major opcode from an instruction.  */
 #define PPC_OP(i) (((i) >> 26) & 0x3f)