Remove i860, i960, bout and aout-adobe targets

Plus remove a few leftovers from the 29k support. include/ * aout/adobe.h: Delete. * aout/reloc.h: Delete. * coff/i860.h: Delete. * coff/i960.h: Delete. * elf/i860.h: Delete. * elf/i960.h: Delete. * opcode/i860.h: Delete. * opcode/i960.h: Delete. * aout/aout64.h (enum reloc_type): Trim off 29k and other unused values. * aout/ar.h (ARMAGB): Remove. * coff/internal.h (struct internal_aouthdr, struct internal_scnhdr, union internal_auxent): Remove i960 support. bfd/ * aout-adobe.c: Delete. * bout.c: Delete. * coff-i860.c: Delete. * coff-i960.c: Delete. * cpu-i860.c: Delete. * cpu-i960.c: Delete. * elf32-i860.c: Delete. * elf32-i960.c: Delete. * hosts/i860mach3.h: Delete. * Makefile.am: Remove i860, i960, bout, and adobe support. * archures.c: Remove i860 and i960 support. * coffcode.h: Likewise. * reloc.c: Likewise. * aoutx.h: Comment updates. * archive.c: Remove BOUT and i960 support. * bfd.c: Remove BOUT support. * coffswap.h: Remove i960 support. * config.bfd: Remove i860, i960 and adobe targets. * configure.ac: Remove adode, bout, i860, i960, icoff targets. * targets.c: Likewise. * ieee.c: Remove i960 support. * mach-o.c: Remove i860 support. * Makefile.in: Regenerate. * bfd-in2.h: Regenerate. * configure: Regenerate. * libbfd.h: Regenerate. * po/SRC-POTFILES.in: Regenerate. opcodes/ * opcodes/i860-dis.c: Delete. * opcodes/i960-dis.c: Delete. * Makefile.am: Remove i860 and i960 support. * configure.ac: Likewise. * disassemble.c: Likewise. * disassemble.h: Likewise. * Makefile.in: Regenerate. * configure: Regenerate. * po/POTFILES.in: Regenerate. binutils/ * ieee.c: Remove i960 support. * od-macho.c: Remove i860 support. * readelf.c: Remove i860 and i960 support. * testsuite/binutils-all/objcopy.exp: Likewise. * testsuite/binutils-all/objdump.exp: Likewise. * testsuite/lib/binutils-common.exp: Likewise. gas/ * config/aout_gnu.h: Delete. * config/tc-i860.c: Delete. * config/tc-i860.h: Delete. * config/tc-i960.c: Delete. * config/tc-i960.h: Delete. * doc/c-i860.texi: Delete. * doc/c-i960.texi: Delete. * testsuite/gas/i860/README.i860: Delete. * testsuite/gas/i860/bitwise.d: Delete. * testsuite/gas/i860/bitwise.s: Delete. * testsuite/gas/i860/branch.d: Delete. * testsuite/gas/i860/branch.s: Delete. * testsuite/gas/i860/bte.d: Delete. * testsuite/gas/i860/bte.s: Delete. * testsuite/gas/i860/dir-align01.d: Delete. * testsuite/gas/i860/dir-align01.s: Delete. * testsuite/gas/i860/dir-intel01.d: Delete. * testsuite/gas/i860/dir-intel01.s: Delete. * testsuite/gas/i860/dir-intel02.d: Delete. * testsuite/gas/i860/dir-intel02.s: Delete. * testsuite/gas/i860/dir-intel03-err.l: Delete. * testsuite/gas/i860/dir-intel03-err.s: Delete. * testsuite/gas/i860/dual01.d: Delete. * testsuite/gas/i860/dual01.s: Delete. * testsuite/gas/i860/dual02-err.l: Delete. * testsuite/gas/i860/dual02-err.s: Delete. * testsuite/gas/i860/dual03.d: Delete. * testsuite/gas/i860/dual03.s: Delete. * testsuite/gas/i860/fldst01.d: Delete. * testsuite/gas/i860/fldst01.s: Delete. * testsuite/gas/i860/fldst02.d: Delete. * testsuite/gas/i860/fldst02.s: Delete. * testsuite/gas/i860/fldst03.d: Delete. * testsuite/gas/i860/fldst03.s: Delete. * testsuite/gas/i860/fldst04.d: Delete. * testsuite/gas/i860/fldst04.s: Delete. * testsuite/gas/i860/fldst05.d: Delete. * testsuite/gas/i860/fldst05.s: Delete. * testsuite/gas/i860/fldst06.d: Delete. * testsuite/gas/i860/fldst06.s: Delete. * testsuite/gas/i860/fldst07.d: Delete. * testsuite/gas/i860/fldst07.s: Delete. * testsuite/gas/i860/fldst08.d: Delete. * testsuite/gas/i860/fldst08.s: Delete. * testsuite/gas/i860/float01.d: Delete. * testsuite/gas/i860/float01.s: Delete. * testsuite/gas/i860/float02.d: Delete. * testsuite/gas/i860/float02.s: Delete. * testsuite/gas/i860/float03.d: Delete. * testsuite/gas/i860/float03.s: Delete. * testsuite/gas/i860/float04.d: Delete. * testsuite/gas/i860/float04.s: Delete. * testsuite/gas/i860/form.d: Delete. * testsuite/gas/i860/form.s: Delete. * testsuite/gas/i860/i860.exp: Delete. * testsuite/gas/i860/iarith.d: Delete. * testsuite/gas/i860/iarith.s: Delete. * testsuite/gas/i860/ldst01.d: Delete. * testsuite/gas/i860/ldst01.s: Delete. * testsuite/gas/i860/ldst02.d: Delete. * testsuite/gas/i860/ldst02.s: Delete. * testsuite/gas/i860/ldst03.d: Delete. * testsuite/gas/i860/ldst03.s: Delete. * testsuite/gas/i860/ldst04.d: Delete. * testsuite/gas/i860/ldst04.s: Delete. * testsuite/gas/i860/ldst05.d: Delete. * testsuite/gas/i860/ldst05.s: Delete. * testsuite/gas/i860/ldst06.d: Delete. * testsuite/gas/i860/ldst06.s: Delete. * testsuite/gas/i860/pfam.d: Delete. * testsuite/gas/i860/pfam.s: Delete. * testsuite/gas/i860/pfmam.d: Delete. * testsuite/gas/i860/pfmam.s: Delete. * testsuite/gas/i860/pfmsm.d: Delete. * testsuite/gas/i860/pfmsm.s: Delete. * testsuite/gas/i860/pfsm.d: Delete. * testsuite/gas/i860/pfsm.s: Delete. * testsuite/gas/i860/pseudo-ops01.d: Delete. * testsuite/gas/i860/pseudo-ops01.s: Delete. * testsuite/gas/i860/regress01.d: Delete. * testsuite/gas/i860/regress01.s: Delete. * testsuite/gas/i860/shift.d: Delete. * testsuite/gas/i860/shift.s: Delete. * testsuite/gas/i860/simd.d: Delete. * testsuite/gas/i860/simd.s: Delete. * testsuite/gas/i860/system.d: Delete. * testsuite/gas/i860/system.s: Delete. * testsuite/gas/i860/xp.d: Delete. * testsuite/gas/i860/xp.s: Delete. * Makefile.am: Remove i860 and i960 support. * configure.tgt: Likewise. * doc/Makefile.am: Likewise. * doc/all.texi: Likewise. * testsuite/gas/all/gas.exp * config/obj-coff.h: Remove i960 support. * doc/internals.texi: Likewise. * expr.c: Likewise. * read.c: Likewise. * write.c: Likewise. * write.h: Likewise. * testsuite/gas/lns/lns.exp: Likewise. * testsuite/gas/symver/symver.exp: Likewise. * config/tc-m68k.c: Remove BOUT support. * config/tc-score.c: Likewise. * config/tc-score7.c: Likewise. * config/tc-sparc.c: Likewise. * symbols.c: Likewise. * doc/h8.texi: Likewise. * configure.ac: Remove BOUT and i860 support. * doc/as.texinfo: Remove BOUT, i860 and i960 support * Makefile.in: Regenerate. * config.in: Regenerate. * configure: Regenerate. * doc/Makefile.in: Regenerate. * po/POTFILES.in: Regenerate. ld/ * emulparams/coff_i860.sh: Delete. * emulparams/elf32_i860.sh: Delete. * emulparams/elf32_i960.sh: Delete. * emulparams/gld960.sh: Delete. * emulparams/gld960coff.sh: Delete. * emulparams/lnk960.sh: Delete. * emultempl/gld960.em: Delete. * emultempl/gld960c.em: Delete. * emultempl/lnk960.em: Delete. * scripttempl/i860coff.sc: Delete. * scripttempl/i960.sc: Delete. * ld.texinfo: Remove i960 support. * Makefile.am: Remove i860 and i960 support. * configure.tgt: Likewise. * testsuite/ld-discard/extern.d: Likewise. * testsuite/ld-discard/start.d: Likewise. * testsuite/ld-discard/static.d: Likewise. * testsuite/ld-elf/compressed1d.d: Likewise. * testsuite/ld-elf/group1.d: Likewise. * testsuite/ld-elf/group3b.d: Likewise. * testsuite/ld-elf/group8a.d: Likewise. * testsuite/ld-elf/group8b.d: Likewise. * testsuite/ld-elf/group9a.d: Likewise. * testsuite/ld-elf/group9b.d: Likewise. * testsuite/ld-elf/linkonce2.d: Likewise. * testsuite/ld-elf/merge.d: Likewise. * testsuite/ld-elf/merge2.d: Likewise. * testsuite/ld-elf/merge3.d: Likewise. * testsuite/ld-elf/orphan-10.d: Likewise. * testsuite/ld-elf/orphan-11.d: Likewise. * testsuite/ld-elf/orphan-12.d: Likewise. * testsuite/ld-elf/orphan-9.d: Likewise. * testsuite/ld-elf/orphan-region.d: Likewise. * testsuite/ld-elf/orphan.d: Likewise. * testsuite/ld-elf/orphan3.d: Likewise. * testsuite/ld-elf/pr12851.d: Likewise. * testsuite/ld-elf/pr12975.d: Likewise. * testsuite/ld-elf/pr13177.d: Likewise. * testsuite/ld-elf/pr13195.d: Likewise. * testsuite/ld-elf/pr17550a.d: Likewise. * testsuite/ld-elf/pr17550b.d: Likewise. * testsuite/ld-elf/pr17550c.d: Likewise. * testsuite/ld-elf/pr17550d.d: Likewise. * testsuite/ld-elf/pr17615.d: Likewise. * testsuite/ld-elf/pr20528a.d: Likewise. * testsuite/ld-elf/pr20528b.d: Likewise. * testsuite/ld-elf/pr21562a.d: Likewise. * testsuite/ld-elf/pr21562b.d: Likewise. * testsuite/ld-elf/pr21562c.d: Likewise. * testsuite/ld-elf/pr21562d.d: Likewise. * testsuite/ld-elf/pr21562i.d: Likewise. * testsuite/ld-elf/pr21562j.d: Likewise. * testsuite/ld-elf/pr21562k.d: Likewise. * testsuite/ld-elf/pr21562l.d: Likewise. * testsuite/ld-elf/pr21562m.d: Likewise. * testsuite/ld-elf/pr21562n.d: Likewise. * testsuite/ld-elf/pr22677.d: Likewise. * testsuite/ld-elf/pr22836-1a.d: Likewise. * testsuite/ld-elf/pr22836-1b.d: Likewise. * testsuite/ld-elf/pr349.d: Likewise. * testsuite/ld-elf/sec-to-seg.exp: Likewise. * testsuite/ld-elf/sec64k.exp: Likewise. * testsuite/ld-elf/warn1.d: Likewise. * testsuite/ld-elf/warn2.d: Likewise. * testsuite/ld-elf/warn3.d: Likewise. * testsuite/lib/ld-lib.exp: Likewise. * Makefile.in: Regenerate. * po/BLD-POTFILES.in: Regenerate.
author: Alan Modra <amodra@gmail.com> 2018-04-11 18:46:05 +0930
committer: Alan Modra <amodra@gmail.com> 2018-04-11 21:49:30 +0930
commit: a8eb42a8b7d48ff6bd12ac83b0e31967b4f5abf1 (patch)
tree: 60b19da93f47532605aea14cc4cec88b442c43f6 /include
parent: c43b2c546be1fead208b816b59c8bdcdf9562571 (diff)
download: fsf-binutils-gdb-a8eb42a8b7d48ff6bd12ac83b0e31967b4f5abf1.zip
fsf-binutils-gdb-a8eb42a8b7d48ff6bd12ac83b0e31967b4f5abf1.tar.gz
fsf-binutils-gdb-a8eb42a8b7d48ff6bd12ac83b0e31967b4f5abf1.tar.bz2
12 files changed, 16 insertions, 1973 deletions
diff --git a/include/ChangeLog b/include/ChangeLog
index 74e6a53..41d785a 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,18 @@
+2018-04-11  Alan Modra  <amodra@gmail.com>
+
+	* aout/adobe.h: Delete.
+	* aout/reloc.h: Delete.
+	* coff/i860.h: Delete.
+	* coff/i960.h: Delete.
+	* elf/i860.h: Delete.
+	* elf/i960.h: Delete.
+	* opcode/i860.h: Delete.
+	* opcode/i960.h: Delete.
+	* aout/aout64.h (enum reloc_type): Trim off 29k and other unused values.
+	* aout/ar.h (ARMAGB): Remove.
+	* coff/internal.h (struct internal_aouthdr, struct internal_scnhdr,
+	union internal_auxent): Remove i960 support.
+
 2018-04-09  Alan Modra  <amodra@gmail.com>
 
 	* elf/ppc.h (R_PPC_PLTSEQ, R_PPC_PLTCALL): Define.
diff --git a/include/aout/adobe.h b/include/aout/adobe.h
deleted file mode 100644
index 33770f9..0000000
--- a/include/aout/adobe.h
+++ /dev/null
@@ -1,319 +0,0 @@
-/* `a.out.adobe' differences from standard a.out files
-
-   Copyright (C) 2001-2018 Free Software Foundation, Inc.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 3 of the License, or
-   (at your option) any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; if not, write to the Free Software
-   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
-   MA 02110-1301, USA.  */
-
-#ifndef __A_OUT_ADOBE_H__
-#define __A_OUT_ADOBE_H__
-
-#define	BYTES_IN_WORD	4
-
-/* Struct external_exec is the same.  */
-
-/* This is the layout on disk of the 32-bit or 64-bit exec header.  */
-
-struct external_exec 
-{
-  bfd_byte e_info[4];		    /* Magic number and stuff.  */
-  bfd_byte e_text[BYTES_IN_WORD];   /* Length of text section in bytes.  */
-  bfd_byte e_data[BYTES_IN_WORD];   /* Length of data section in bytes.  */
-  bfd_byte e_bss[BYTES_IN_WORD];    /* Length of bss area in bytes.  */
-  bfd_byte e_syms[BYTES_IN_WORD];   /* Length of symbol table in bytes.  */
-  bfd_byte e_entry[BYTES_IN_WORD];  /* Start address.  */
-  bfd_byte e_trsize[BYTES_IN_WORD]; /* Length of text relocation info.  */
-  bfd_byte e_drsize[BYTES_IN_WORD]; /* Length of data relocation info.  */
-};
-
-#define	EXEC_BYTES_SIZE	(4 + BYTES_IN_WORD * 7)
-
-/* Magic numbers for a.out files.  */
-
-#undef	ZMAGIC
-#define	ZMAGIC	0xAD0BE		/* Cute, eh?  */
-#undef	OMAGIC
-#undef	NMAGIC
-
-#define N_BADMAG(x)	  ((x)->a_info != ZMAGIC)
-
-/* By default, segment size is constant.  But some machines override this
-   to be a function of the a.out header (e.g. machine type).  */
-#ifndef	N_SEGSIZE
-#define	N_SEGSIZE(x)	SEGMENT_SIZE
-#endif
-#undef N_SEGSIZE   /* FIXMEXXXX */
-
-/* Segment information for the a.out.Adobe format is specified after the
-   file header.  It contains N segment descriptors, followed by one with
-   a type of zero.  
-
-   The actual text of the segments starts at N_TXTOFF in the file,
-   regardless of how many or how few segment headers there are.  */
-
-struct external_segdesc
-{
-  unsigned char e_type[1];
-  unsigned char e_size[3];
-  unsigned char e_virtbase[4];
-  unsigned char e_filebase[4];
-};
-
-struct internal_segdesc
-{
-  unsigned int	a_type:8;	/* Segment type N_TEXT, N_DATA, 0.  */
-  unsigned int 	a_size:24;	/* Segment size.  */
-  bfd_vma	a_virtbase;	/* Virtual address.  */
-  unsigned int	a_filebase;	/* Base address in object file.  */
-};
-
-#define N_TXTADDR(x) is_this_really_unused?
-
-/* This is documented to be at 1024, but appears to really be at 2048.
-   FIXME?!  */
-#define N_TXTOFF(x)	2048
-
-#define	N_TXTSIZE(x) ((x)->a_text)
-
-#define N_DATADDR(x) is_this_really_unused?
-
-#define N_BSSADDR(x) is_this_really_unused?
-
-/* Offsets of the various portions of the file after the text segment.  */
-
-#define N_DATOFF(x)	( N_TXTOFF(x) + N_TXTSIZE(x) )
-#define N_TRELOFF(x)	( N_DATOFF(x) + (x)->a_data )
-#define N_DRELOFF(x)	( N_TRELOFF(x) + (x)->a_trsize )
-#define N_SYMOFF(x)	( N_DRELOFF(x) + (x)->a_drsize )
-#define N_STROFF(x)	( N_SYMOFF(x) + (x)->a_syms )
-
-/* Symbols.  */
-struct external_nlist
-{
-  bfd_byte e_strx[BYTES_IN_WORD];	/* Index into string table of name.  */
-  bfd_byte e_type[1];			/* Type of symbol.  */
-  bfd_byte e_other[1];			/* Misc info (usually empty).  */
-  bfd_byte e_desc[2];			/* Description field.  */
-  bfd_byte e_value[BYTES_IN_WORD];	/* Value of symbol.  */
-};
-
-#define EXTERNAL_NLIST_SIZE (BYTES_IN_WORD+4+BYTES_IN_WORD)
-
-struct internal_nlist
-{
-  unsigned long n_strx;			/* Index into string table of name.  */
-  unsigned char n_type;			/* Type of symbol.  */
-  unsigned char n_other;		/* Misc info (usually empty).  */
-  unsigned short n_desc;		/* Description field.  */
-  bfd_vma n_value;			/* Value of symbol.  */
-};
-
-/* The n_type field is the symbol type, containing:  */
-
-#define N_UNDF	0	/* Undefined symbol.  */
-#define N_ABS 	2	/* Absolute symbol -- defined at particular addr.  */
-#define N_TEXT 	4	/* Text sym -- defined at offset in text seg.  */
-#define N_DATA 	6	/* Data sym -- defined at offset in data seg.  */
-#define N_BSS 	8	/* BSS  sym -- defined at offset in zero'd seg.  */
-#define	N_COMM	0x12	/* Common symbol (visible after shared lib dynlink).  */
-#define N_FN	0x1f	/* File name of .o file.  */
-#define	N_FN_SEQ 0x0C	/* N_FN from Sequent compilers (sigh).  */
-/* Note: N_EXT can only be usefully OR-ed with N_UNDF, N_ABS, N_TEXT,
-   N_DATA, or N_BSS.  When the low-order bit of other types is set,
-   (e.g. N_WARNING versus N_FN), they are two different types.  */
-#define N_EXT 	1	/* External symbol (as opposed to local-to-this-file).  */
-#define N_TYPE  0x1e
-#define N_STAB 	0xe0	/* If any of these bits are on, it's a debug symbol.  */
-
-#define N_INDR 0x0a
-
-/* The following symbols refer to set elements.
-   All the N_SET[ATDB] symbols with the same name form one set.
-   Space is allocated for the set in the text section, and each set
-   elements value is stored into one word of the space.
-   The first word of the space is the length of the set (number of elements).
-
-   The address of the set is made into an N_SETV symbol
-   whose name is the same as the name of the set.
-   This symbol acts like a N_DATA global symbol
-   in that it can satisfy undefined external references.  */
-
-/* These appear as input to LD, in a .o file.  */
-#define	N_SETA	0x14		/* Absolute set element symbol.  */
-#define	N_SETT	0x16		/* Text set element symbol.  */
-#define	N_SETD	0x18		/* Data set element symbol.  */
-#define	N_SETB	0x1A		/* Bss set element symbol.  */
-
-/* This is output from LD.  */
-#define N_SETV	0x1C		/* Pointer to set vector in data area.  */
-
-/* Warning symbol. The text gives a warning message, the next symbol
-   in the table will be undefined. When the symbol is referenced, the
-   message is printed.  */
-
-#define	N_WARNING 0x1e
-
-/* Relocations 
-
-  There	are two types of relocation flavours for a.out systems,
-  standard and extended. The standard form is used on systems where the
-  instruction has room for all the bits of an offset to the operand, whilst
-  the extended form is used when an address operand has to be split over n
-  instructions. Eg, on the 68k, each move instruction can reference
-  the target with a displacement of 16 or 32 bits. On the sparc, move
-  instructions use an offset of 14 bits, so the offset is stored in
-  the reloc field, and the data in the section is ignored.  */
-
-/* This structure describes a single relocation to be performed.
-   The text-relocation section of the file is a vector of these structures,
-   all of which apply to the text section.
-   Likewise, the data-relocation section applies to the data section.  */
-
-struct reloc_std_external
-{
-  bfd_byte r_address[BYTES_IN_WORD];	/* Offset of data to relocate.  */
-  bfd_byte r_index[3];			/* Symbol table index of symbol.  */
-  bfd_byte r_type[1];			/* Relocation type.  */
-};
-
-#define	RELOC_STD_BITS_PCREL_BIG	0x80
-#define	RELOC_STD_BITS_PCREL_LITTLE	0x01
-
-#define	RELOC_STD_BITS_LENGTH_BIG	0x60
-#define	RELOC_STD_BITS_LENGTH_SH_BIG	5	/* To shift to units place.  */
-#define	RELOC_STD_BITS_LENGTH_LITTLE	0x06
-#define	RELOC_STD_BITS_LENGTH_SH_LITTLE	1
-
-#define	RELOC_STD_BITS_EXTERN_BIG	0x10
-#define	RELOC_STD_BITS_EXTERN_LITTLE	0x08
-
-#define	RELOC_STD_BITS_BASEREL_BIG	0x08
-#define	RELOC_STD_BITS_BASEREL_LITTLE	0x08
-
-#define	RELOC_STD_BITS_JMPTABLE_BIG	0x04
-#define	RELOC_STD_BITS_JMPTABLE_LITTLE	0x04
-
-#define	RELOC_STD_BITS_RELATIVE_BIG	0x02
-#define	RELOC_STD_BITS_RELATIVE_LITTLE	0x02
-
-#define	RELOC_STD_SIZE	(BYTES_IN_WORD + 3 + 1)		/* Bytes per relocation entry.  */
-
-struct reloc_std_internal
-{
-  bfd_vma r_address;		/* Address (within segment) to be relocated.  */
-  /* The meaning of r_symbolnum depends on r_extern.  */
-  unsigned int r_symbolnum:24;
-  /* Nonzero means value is a pc-relative offset
-     and it should be relocated for changes in its own address
-     as well as for changes in the symbol or section specified.  */
-  unsigned int r_pcrel:1;
-  /* Length (as exponent of 2) of the field to be relocated.
-     Thus, a value of 2 indicates 1<<2 bytes.  */
-  unsigned int r_length:2;
-  /* 1 => relocate with value of symbol.
-     r_symbolnum is the index of the symbol
-     in files the symbol table.
-     0 => relocate with the address of a segment.
-     r_symbolnum is N_TEXT, N_DATA, N_BSS or N_ABS
-     (the N_EXT bit may be set also, but signifies nothing).  */
-  unsigned int r_extern:1;
-  /* The next three bits are for SunOS shared libraries, and seem to
-     be undocumented.  */
-  unsigned int r_baserel:1;	/* Linkage table relative.  */
-  unsigned int r_jmptable:1;	/* pc-relative to jump table.  */
-  unsigned int r_relative:1;	/* "relative relocation".  */
-  /* unused */
-  unsigned int r_pad:1;		/* Padding -- set to zero.  */
-};
-
-
-/* EXTENDED RELOCS  */
-
-struct reloc_ext_external
-{
-  bfd_byte r_address[BYTES_IN_WORD];	/* Offset of data to relocate.  */
-  bfd_byte r_index[3];			/* Symbol table index of symbol.  */
-  bfd_byte r_type[1];			/* Relocation type.  */
-  bfd_byte r_addend[BYTES_IN_WORD];	/* Datum addend.  */
-};
-
-#define	RELOC_EXT_BITS_EXTERN_BIG	0x80
-#define	RELOC_EXT_BITS_EXTERN_LITTLE	0x01
-
-#define	RELOC_EXT_BITS_TYPE_BIG		0x1F
-#define	RELOC_EXT_BITS_TYPE_SH_BIG	0
-#define	RELOC_EXT_BITS_TYPE_LITTLE	0xF8
-#define	RELOC_EXT_BITS_TYPE_SH_LITTLE	3
-
-/* Bytes per relocation entry */
-#define	RELOC_EXT_SIZE	(BYTES_IN_WORD + 3 + 1 + BYTES_IN_WORD)
-
-enum reloc_type
-{
-  /* Simple relocations.  */
-  RELOC_8,			/* data[0:7] = addend + sv 		*/
-  RELOC_16,			/* data[0:15] = addend + sv 		*/
-  RELOC_32,			/* data[0:31] = addend + sv 		*/
-  /* PC-rel displacement.  */
-  RELOC_DISP8,			/* data[0:7] = addend - pc + sv 	*/
-  RELOC_DISP16,			/* data[0:15] = addend - pc + sv 	*/
-  RELOC_DISP32,			/* data[0:31] = addend - pc + sv 	*/
-  /* Special.  */
-  RELOC_WDISP30,		/* data[0:29] = (addend + sv - pc)>>2 	*/
-  RELOC_WDISP22,		/* data[0:21] = (addend + sv - pc)>>2 	*/
-  RELOC_HI22,			/* data[0:21] = (addend + sv)>>10 	*/
-  RELOC_22,			/* data[0:21] = (addend + sv) 		*/
-  RELOC_13,			/* data[0:12] = (addend + sv)		*/
-  RELOC_LO10,			/* data[0:9] = (addend + sv)		*/
-  RELOC_SFA_BASE,		
-  RELOC_SFA_OFF13,
-  /* P.I.C. (base-relative).  */
-  RELOC_BASE10,  		/* Not sure - maybe we can do this the  */
-  RELOC_BASE13,			/* right way now.  */
-  RELOC_BASE22,
-  /* For some sort of pc-rel P.I.C. (?)  */
-  RELOC_PC10,
-  RELOC_PC22,
-  /* P.I.C. jump table.  */
-  RELOC_JMP_TBL,
-  /* Reputedly for shared libraries somehow.  */
-  RELOC_SEGOFF16,
-  RELOC_GLOB_DAT,
-  RELOC_JMP_SLOT,
-  RELOC_RELATIVE,
-
-  RELOC_11,	
-  RELOC_WDISP2_14,
-  RELOC_WDISP19,
-  RELOC_HHI22,			/* data[0:21] = (addend + sv) >> 42     */
-  RELOC_HLO10,			/* data[0:9] = (addend + sv) >> 32      */
-  
-  /* 29K relocation types */
-  RELOC_JUMPTARG,
-  RELOC_CONST,
-  RELOC_CONSTH,
-  
-  NO_RELOC
-};
-
-struct reloc_internal
-{
-  bfd_vma r_address;		/* Offset of data to relocate.  */
-  long	r_index;		/* Symbol table index of symbol.  */
-  enum reloc_type r_type;	/* Relocation type.  */
-  bfd_vma r_addend;		/* Datum addend.  */
-};
-
-#endif	/* __A_OUT_ADOBE_H__ */
diff --git a/include/aout/aout64.h b/include/aout/aout64.h
index 0e7ced7..a0827d5 100644
--- a/include/aout/aout64.h
+++ b/include/aout/aout64.h
@@ -476,25 +476,7 @@ enum reloc_type
   RELOC_11,	
   RELOC_WDISP2_14,
   RELOC_WDISP19,
-  RELOC_HHI22,			/* data[0:21] = (addend + sv) >> 42     */
-  RELOC_HLO10,			/* data[0:9] = (addend + sv) >> 32      */
-  
-  /* 29K relocation types.  */
-  RELOC_JUMPTARG,
-  RELOC_CONST,
-  RELOC_CONSTH,
-  
-  /* All the new ones I can think of, for sparc v9.  */
-  RELOC_64,			/* data[0:63] = addend + sv 		*/
-  RELOC_DISP64,			/* data[0:63] = addend - pc + sv 	*/
-  RELOC_WDISP21,		/* data[0:20] = (addend + sv - pc)>>2 	*/
-  RELOC_DISP21,			/* data[0:20] = addend - pc + sv        */
-  RELOC_DISP14,			/* data[0:13] = addend - pc + sv 	*/
-  /* Q .
-     What are the other ones,
-     Since this is a clean slate, can we throw away the ones we dont
-     understand ? Should we sort the values ? What about using a
-     microcode format like the 68k ?  */
+
   NO_RELOC
   };
 
diff --git a/include/aout/ar.h b/include/aout/ar.h
index d9e3bc6..905fcbc 100644
--- a/include/aout/ar.h
+++ b/include/aout/ar.h
@@ -28,7 +28,6 @@
    compatible with existing BSDish archives. */
 
 #define ARMAG  "!<arch>\012"	/* For COFF and a.out archives.  */
-#define ARMAGB "!<bout>\012"	/* For b.out archives.  */
 #define ARMAGT "!<thin>\012"	/* For thin archives.  */
 #define SARMAG 8
 #define ARFMAG "`\012"
diff --git a/include/aout/reloc.h b/include/aout/reloc.h
deleted file mode 100644
index 2249107f..0000000
--- a/include/aout/reloc.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/* reloc.h -- Header file for relocation information.
-   Copyright (C) 1989-2018 Free Software Foundation, Inc.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 3 of the License, or
-   (at your option) any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; if not, write to the Free Software
-   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
-   MA 02110-1301, USA.  */
-
-/* Relocation types for a.out files using reloc_info_extended
-   (SPARC and AMD 29000). */
-
-#ifndef _RELOC_H_READ_
-#define _RELOC_H_READ_ 1
-
-enum reloc_type
-  {
-    RELOC_8,        RELOC_16,        RELOC_32, /* simple relocations */
-    RELOC_DISP8,    RELOC_DISP16,    RELOC_DISP32, /* pc-rel displacement */
-    RELOC_WDISP30,  RELOC_WDISP22,
-    RELOC_HI22,     RELOC_22,
-    RELOC_13,       RELOC_LO10,
-    RELOC_SFA_BASE, RELOC_SFA_OFF13,
-    RELOC_BASE10,   RELOC_BASE13,    RELOC_BASE22, /* P.I.C. (base-relative) */
-    RELOC_PC10,     RELOC_PC22,	/* for some sort of pc-rel P.I.C. (?) */
-    RELOC_JMP_TBL,		/* P.I.C. jump table */
-    RELOC_SEGOFF16,		/* reputedly for shared libraries somehow */
-    RELOC_GLOB_DAT,  RELOC_JMP_SLOT, RELOC_RELATIVE,
-    RELOC_11,
-    RELOC_WDISP2_14,
-    RELOC_WDISP19,
-    RELOC_HHI22,
-    RELOC_HLO10,
-    
-    /* 29K relocation types */
-    RELOC_JUMPTARG, RELOC_CONST,     RELOC_CONSTH,
-    
-    RELOC_WDISP14, RELOC_WDISP21,
-    
-    NO_RELOC
-    };
-
-#define	RELOC_TYPE_NAMES \
-"8",		"16",		"32",		"DISP8",	\
-"DISP16",	"DISP32",	"WDISP30",	"WDISP22",	\
-"HI22",		"22",		"13",		"LO10",		\
-"SFA_BASE",	"SFAOFF13",	"BASE10",	"BASE13",	\
-"BASE22",	"PC10",		"PC22",		"JMP_TBL",	\
-"SEGOFF16",	"GLOB_DAT",	"JMP_SLOT",	"RELATIVE",	\
-"11",		"WDISP2_14",	"WDISP19", 	"HHI22",	\
-"HLO10",							\
-"JUMPTARG",	"CONST",	"CONSTH",	"WDISP14",	\
-"WDISP21",	\
-"NO_RELOC"
-
-#endif /* _RELOC_H_READ_ */
-
-/* end of reloc.h */
diff --git a/include/coff/i860.h b/include/coff/i860.h
deleted file mode 100644
index 3afa38f..0000000
--- a/include/coff/i860.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/* COFF information for the Intel i860.
-   
-   Copyright (C) 2001-2018 Free Software Foundation, Inc.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 3 of the License, or
-   (at your option) any later version.
-   
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-   
-   You should have received a copy of the GNU General Public License
-   along with this program; if not, write to the Free Software
-   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
-   MA 02110-1301, USA.  */
-
-/* This file was hacked from i386.h   [dolan@ssd.intel.com] */
-
-#define L_LNNO_SIZE 2
-#include "coff/external.h"
-
-/* Bits for f_flags:
- 	F_RELFLG	relocation info stripped from file
- 	F_EXEC		file is executable (no unresolved external references)
- 	F_LNNO		line numbers stripped from file
- 	F_LSYMS		local symbols stripped from file
- 	F_AR32WR	file has byte ordering of an AR32WR machine (e.g. vax).  */
-
-#define F_RELFLG	(0x0001)
-#define F_EXEC		(0x0002)
-#define F_LNNO		(0x0004)
-#define F_LSYMS		(0x0008)
-
-#define	I860MAGIC	0x14d
-
-#define I860BADMAG(x)   ((x).f_magic != I860MAGIC)
-
-#undef AOUTSZ
-#define AOUTSZ 36
-
-/* FIXME: What are the a.out magic numbers?  */
-
-#define _ETEXT	"etext"
-
-/********************** RELOCATION DIRECTIVES **********************/
-
-struct external_reloc
-{
-  char r_vaddr[4];
-  char r_symndx[4];
-  char r_type[2];
-};
-
-#define RELOC struct external_reloc
-#define RELSZ 10
-
-/* The relocation directory entry types.
-     PAIR   : The low half that follows relates to the preceding HIGH[ADJ].
-     HIGH   : The high half of a 32-bit constant.
-     LOWn   : The low half, insn bits 15..(n-1), 2^n-byte aligned. 
-     SPLITn : The low half, insn bits 20..16 and 10..(n-1), 2^n-byte aligned. 
-     HIGHADJ: Similar to HIGH, but with adjustment.
-     BRADDR : 26-bit branch displacement.
-
-   Note: The Intel assembler manual lists LOW4 as one of the
-   relocation types, but it appears to be useless for the i860.
-   We will recognize it anyway, just in case it actually appears in
-   any object files.  */
-
-enum {
-  COFF860_R_PAIR	= 0x1c,
-  COFF860_R_HIGH	= 0x1e,
-  COFF860_R_LOW0	= 0x1f,
-  COFF860_R_LOW1	= 0x20,
-  COFF860_R_LOW2	= 0x21,
-  COFF860_R_LOW3	= 0x22,
-  COFF860_R_LOW4	= 0x23,
-  COFF860_R_SPLIT0	= 0x24,
-  COFF860_R_SPLIT1	= 0x25,
-  COFF860_R_SPLIT2	= 0x26,
-  COFF860_R_HIGHADJ	= 0x27,
-  COFF860_R_BRADDR	= 0x28
-};
-
diff --git a/include/coff/i960.h b/include/coff/i960.h
deleted file mode 100644
index 19d35f9..0000000
--- a/include/coff/i960.h
+++ /dev/null
@@ -1,320 +0,0 @@
-/* coff information for 80960.  Origins: Intel corp, natch.
-   
-   Copyright (C) 2001-2018 Free Software Foundation, Inc.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 3 of the License, or
-   (at your option) any later version.
-   
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-   
-   You should have received a copy of the GNU General Public License
-   along with this program; if not, write to the Free Software
-   Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
-   MA 02110-1301, USA.  */
-
-/* NOTE: Tagentries (cf TAGBITS) are no longer used by the 960 */
-
-/********************** FILE HEADER **********************/
-
-struct external_filehdr
-{
-  char f_magic[2];	/* magic number			*/
-  char f_nscns[2];	/* number of sections		*/
-  char f_timdat[4];	/* time & date stamp		*/
-  char f_symptr[4];	/* file pointer to symtab	*/
-  char f_nsyms[4];	/* number of symtab entries	*/
-  char f_opthdr[2];	/* sizeof(optional hdr)		*/
-  char f_flags[2];	/* flags			*/
-};
-
-#define OMAGIC      (0407)	/* old impure format. data immediately
-                                   follows text. both sections are rw. */
-#define NMAGIC      (0410)	/* split i&d, read-only text */
-
-/*
-*	Intel 80960 (I960) processor flags.
-*	F_I960TYPE == mask for processor type field. 
-*/
-
-#define	F_I960TYPE	(0xf000)
-#define	F_I960CORE	(0x1000)
-#define	F_I960KB	(0x2000)
-#define	F_I960SB	(0x2000)
-#define	F_I960MC	(0x3000)
-#define	F_I960XA	(0x4000)
-#define	F_I960CA	(0x5000)
-#define	F_I960KA	(0x6000)
-#define	F_I960SA	(0x6000)
-#define F_I960JX	(0x7000)
-#define F_I960HX	(0x8000)
-
-
-/** i80960 Magic Numbers
-*/
-
-#define I960ROMAGIC	(0x160)	/* read-only text segments */
-#define I960RWMAGIC	(0x161)	/* read-write text segments */
-
-#define I960BADMAG(x) (((x).f_magic!=I960ROMAGIC) && ((x).f_magic!=I960RWMAGIC))
-
-#define	FILHDR	struct external_filehdr
-#define	FILHSZ	20
-
-/********************** AOUT "OPTIONAL HEADER" **********************/
-
-typedef struct
-{
-  unsigned long	phys_addr;
-  unsigned long	bitarray;
-} TAGBITS;
-
-typedef struct 
-{
-  char 	magic[2];		/* type of file				*/
-  char	vstamp[2];		/* version stamp			*/
-  char	tsize[4];		/* text size in bytes, padded to FW bdry*/
-  char	dsize[4];		/* initialized data "  "		*/
-  char	bsize[4];		/* uninitialized data "   "		*/
-  char	entry[4];		/* entry pt.				*/
-  char 	text_start[4];		/* base of text used for this file */
-  char 	data_start[4];		/* base of data used for this file */
-  char	tagentries[4];		/* number of tag entries to follow */
-}
-AOUTHDR;
-
-/* return a pointer to the tag bits array */
-
-#define TAGPTR(aout) ((TAGBITS *) (&(aout.tagentries)+1))
-
-/* compute size of a header */
-
-/*#define AOUTSZ(aout) (sizeof(AOUTHDR)+(aout.tagentries*sizeof(TAGBITS)))*/
-#define AOUTSZ 32
-#define AOUTHDRSZ 32
-
-
-/********************** SECTION HEADER **********************/
-
-struct external_scnhdr
-{
-  char		s_name[8];	/* section name			*/
-  char		s_paddr[4];	/* physical address, aliased s_nlib */
-  char		s_vaddr[4];	/* virtual address		*/
-  char		s_size[4];	/* section size			*/
-  char		s_scnptr[4];	/* file ptr to raw data for section */
-  char		s_relptr[4];	/* file ptr to relocation	*/
-  char		s_lnnoptr[4];	/* file ptr to line numbers	*/
-  char		s_nreloc[2];	/* number of relocation entries	*/
-  char		s_nlnno[2];	/* number of line number entries*/
-  char		s_flags[4];	/* flags			*/
-  char 		s_align[4];	/* section alignment		*/
-};
-
-
-#define	SCNHDR	struct external_scnhdr
-#define	SCNHSZ	44
-
-/*
- * names of "special" sections
- */
-#define _TEXT   ".text"
-#define _DATA   ".data"
-#define _BSS    ".bss"
-
-/********************** LINE NUMBERS **********************/
-
-/* 1 line number entry for every "breakpointable" source line in a section.
- * Line numbers are grouped on a per function basis; first entry in a function
- * grouping will have l_lnno = 0 and in place of physical address will be the
- * symbol table index of the function name.
- */
-struct external_lineno
-{
-  union
-  {
-    char l_symndx[4];	/* function name symbol index, iff l_lnno == 0*/
-    char l_paddr[4];	/* (physical) address of line number	*/
-  } l_addr;
-
-  char l_lnno[2];		/* line number		*/
-  char padding[2];	/* force alignment	*/
-};
-
-
-#define	LINENO	struct external_lineno
-#define	LINESZ	8
-
-/********************** SYMBOLS **********************/
-
-#define E_SYMNMLEN	8	/* # characters in a symbol name	*/
-#define E_FILNMLEN	14	/* # characters in a file name		*/
-#define E_DIMNUM	4	/* # array dimensions in auxiliary entry */
-
-struct external_syment 
-{
-  union
-  {
-    char e_name[E_SYMNMLEN];
-
-    struct
-    {
-      char e_zeroes[4];
-      char e_offset[4];
-    } e;
-  } e;
-
-  char e_value[4];
-  char e_scnum[2];
-  char e_flags[2];
-  char e_type[4];
-  char e_sclass[1];
-  char e_numaux[1];
-  char pad2[2];
-};
-
-#define N_BTMASK	(0x1f)
-#define N_TMASK		(0x60)
-#define N_BTSHFT	(5)
-#define N_TSHIFT	(2)
-  
-union external_auxent
-{
-  struct
-  {
-    char x_tagndx[4];	/* str, un, or enum tag indx */
-
-    union
-    {
-      struct
-      {
-	char  x_lnno[2]; /* declaration line number */
-	char  x_size[2]; /* str/union/array size */
-      } x_lnsz;
-
-      char x_fsize[4];	/* size of function */
-
-    } x_misc;
-
-    union
-    {
-      struct 		/* if ISFCN, tag, or .bb */
-      {
-	char x_lnnoptr[4];	/* ptr to fcn line # */
-	char x_endndx[4];	/* entry ndx past block end */
-      } x_fcn;
-
-      struct 		/* if ISARY, up to 4 dimen. */
-      {
-	char x_dimen[E_DIMNUM][2];
-      } x_ary;
-
-    } x_fcnary;
-
-    char x_tvndx[2];		/* tv index */
-
-  } x_sym;
-
-  union
-  {
-    char x_fname[E_FILNMLEN];
-
-    struct
-    {
-      char x_zeroes[4];
-      char x_offset[4];
-    } x_n;
-
-  } x_file;
-
-  struct
-  {
-    char x_scnlen[4];			/* section length */
-    char x_nreloc[2];	/* # relocation entries */
-    char x_nlinno[2];	/* # line numbers */
-
-  } x_scn;
-
-  struct
-  {
-    char x_tvfill[4];	/* tv fill value */
-    char x_tvlen[2];	/* length of .tv */
-    char x_tvran[2][2];	/* tv range */
-
-  } x_tv;		/* info about .tv section (in auxent of symbol .tv)) */
-
-  /******************************************
-   *  I960-specific *2nd* aux. entry formats
-   ******************************************/
-  struct
-  {
-    /* This is a very old typo that keeps getting propagated. */
-#define x_stdindx x_stindx
-    char x_stindx[4];	/* sys. table entry */
-  } x_sc;	/* system call entry */
-
-  struct
-  {
-    char x_balntry[4]; /* BAL entry point */
-  } x_bal; /* BAL-callable function */
-
-  struct
-  {
-    char x_timestamp[4];	        /* time stamp */
-    char 	x_idstring[20];	        /* producer identity string */
-
-  } x_ident;	                        /* Producer ident info */
-};
-
-#define	SYMENT	struct external_syment
-#define	SYMESZ	24
-#define	AUXENT	union external_auxent
-#define	AUXESZ	24
-
-#	define _ETEXT	"_etext"
-
-/********************** RELOCATION DIRECTIVES **********************/
-
-struct external_reloc
-{
-  char r_vaddr[4];
-  char r_symndx[4];
-  char r_type[2];
-  char pad[2];
-};
-
-/* r_type values for the i960.  */
-
-/* The i960 uses R_RELLONG, which is defined in internal.h as 0x11.
-   It is an absolute 32 bit relocation.  */
-
-#define R_IPRMED 	(0x19)	/* 24-bit ip-relative relocation */
-#define R_OPTCALL	(0x1b)	/* 32-bit optimizable call (leafproc/sysproc) */
-#define R_OPTCALLX	(0x1c)	/* 64-bit optimizable call (leafproc/sysproc) */
-
-/* The following relocation types are defined use by relaxing linkers,
-   which convert 32 bit calls (which require a 64 bit instruction)
-   into 24 bit calls (which require a 32 bit instruction) when
-   possible.  It will be possible whenever the target of the call is
-   within a 24 bit range of the call instruction.
-
-   It is always safe to ignore these relocations.  They only serve to
-   mark points which the relaxing linker will have to consider.  The
-   assembler must ensure that the correct code is generated even if
-   the relocations are ignored.  In particular, this means that the
-   R_IPR13 relocation may not appear with an external symbol.  */
-
-#define R_IPR13		(0x1d)	/* 13 bit ip-relative branch */
-#define R_ALIGN		(0x1e)  /* alignment marker.  This has no
-				   associated symbol.  Instead, the
-				   r_symndx field indicates the
-				   require alignment at this point in
-				   the file.  It must be a power of 2.  */
-
-#define RELOC struct external_reloc
-#define RELSZ 12
-
diff --git a/include/coff/internal.h b/include/coff/internal.h
index 81a84c8..2b7737d 100644
--- a/include/coff/internal.h
+++ b/include/coff/internal.h
@@ -257,9 +257,6 @@ struct internal_aouthdr
   bfd_vma text_start;		/* base of text used for this file */
   bfd_vma data_start;		/* base of data used for this file */
 
-  /* i960 stuff */
-  unsigned long tagentries;	/* number of tag entries to follow */
-
   /* RS/6000 stuff */
   bfd_vma o_toc;		/* address of TOC			*/
   short o_snentry;		/* section number for entry point */
@@ -416,7 +413,6 @@ struct internal_scnhdr
   unsigned long s_nreloc;	/* number of relocation entries	*/
   unsigned long s_nlnno;	/* number of line number entries*/
   long s_flags;			/* flags			*/
-  long s_align;			/* used on I960			*/
   unsigned char s_page;         /* TI COFF load page            */
 };
 
@@ -668,28 +664,6 @@ union internal_auxent
 /* 		14	??? */
 #define	XMC_TC0	15		/* Read-write TOC anchor */
 #define XMC_TD	16		/* Read-write data in TOC */
-
-  /******************************************
-   *  I960-specific *2nd* aux. entry formats
-   ******************************************/
-  struct
-  {
-    /* This is a very old typo that keeps getting propagated. */
-#define x_stdindx x_stindx
-    long x_stindx;		/* sys. table entry */
-  }      x_sc;			/* system call entry */
-
-  struct
-  {
-    unsigned long x_balntry;	/* BAL entry point */
-  }      x_bal;			/* BAL-callable function */
-
-  struct
-  {
-    unsigned long x_timestamp;	/* time stamp */
-    char x_idstring[20];	/* producer identity string */
-  }      x_ident;		/* Producer ident info */
-
 };
 
 /********************** RELOCATION DIRECTIVES **********************/
diff --git a/include/elf/i860.h b/include/elf/i860.h
deleted file mode 100644
index 7762c1d..0000000
--- a/include/elf/i860.h
+++ /dev/null
@@ -1,66 +0,0 @@
-/* i860 ELF support for BFD.
-   Copyright (C) 2000-2018 Free Software Foundation, Inc.
-
-   Contributed by Jason Eckhardt <jle@cygnus.com>.
-
-   This file is part of BFD, the Binary File Descriptor library.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 3 of the License, or
-   (at your option) any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; if not, write to the Free Software Foundation,
-   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
-
-#ifndef _ELF_I860_H
-#define _ELF_I860_H
-
-/* Note: i860 ELF is defined to use only RELA relocations.  */
-
-#include "elf/reloc-macros.h"
-
-START_RELOC_NUMBERS (elf_i860_reloc_type)
-     RELOC_NUMBER (R_860_NONE,      0x00)	/* No reloc */
-     RELOC_NUMBER (R_860_32,        0x01)	/* S+A  */
-     RELOC_NUMBER (R_860_COPY,	    0x02)	/* No calculation */
-     RELOC_NUMBER (R_860_GLOB_DAT,  0x03)	/* S, Create GOT entry */
-     RELOC_NUMBER (R_860_JUMP_SLOT, 0x04)	/* S+A, Create PLT entry */
-     RELOC_NUMBER (R_860_RELATIVE,  0x05)	/* B+A, Adj by program base */
-     RELOC_NUMBER (R_860_PC26,      0x30)	/* (S+A-P) >> 2 */ 
-     RELOC_NUMBER (R_860_PLT26,	    0x31)	/* (L+A-P) >> 2 */
-     RELOC_NUMBER (R_860_PC16,      0x32)	/* (S+A-P) >> 2 */
-     RELOC_NUMBER (R_860_LOW0,      0x40)	/* S+A */
-     RELOC_NUMBER (R_860_SPLIT0,    0x42)	/* S+A */       
-     RELOC_NUMBER (R_860_LOW1,      0x44)	/* S+A */
-     RELOC_NUMBER (R_860_SPLIT1,    0x46)	/* S+A */
-     RELOC_NUMBER (R_860_LOW2,      0x48)	/* S+A */
-     RELOC_NUMBER (R_860_SPLIT2,    0x4A)	/* S+A */
-     RELOC_NUMBER (R_860_LOW3,      0x4C)	/* S+A */
-     RELOC_NUMBER (R_860_LOGOT0,    0x50)	/* G */
-     RELOC_NUMBER (R_860_SPGOT0,    0x52)	/* G */
-     RELOC_NUMBER (R_860_LOGOT1,    0x54)	/* G */
-     RELOC_NUMBER (R_860_SPGOT1,    0x56)	/* G */
-     RELOC_NUMBER (R_860_LOGOTOFF0, 0x60)	/* O */
-     RELOC_NUMBER (R_860_SPGOTOFF0, 0x62)	/* O */
-     RELOC_NUMBER (R_860_LOGOTOFF1, 0x64)	/* O */
-     RELOC_NUMBER (R_860_SPGOTOFF1, 0x66)	/* O */
-     RELOC_NUMBER (R_860_LOGOTOFF2, 0x68)	/* O */
-     RELOC_NUMBER (R_860_LOGOTOFF3, 0x6C)	/* O */
-     RELOC_NUMBER (R_860_LOPC,      0x70)	/* (S+A-P) >> 2 */
-     RELOC_NUMBER (R_860_HIGHADJ,   0x80)	/* hiadj(S+A) */
-     RELOC_NUMBER (R_860_HAGOT,     0x90)	/* hiadj(G) */
-     RELOC_NUMBER (R_860_HAGOTOFF,  0xA0)	/* hiadj(O) */
-     RELOC_NUMBER (R_860_HAPC,      0xB0)	/* hiadj((S+A-P) >> 2) */
-     RELOC_NUMBER (R_860_HIGH,      0xC0)	/* (S+A) >> 16 */
-     RELOC_NUMBER (R_860_HIGOT,     0xD0)	/* G >> 16 */
-     RELOC_NUMBER (R_860_HIGOTOFF,  0xE0)	/* O */
-END_RELOC_NUMBERS (R_860_max)
-
-#endif
diff --git a/include/elf/i960.h b/include/elf/i960.h
deleted file mode 100644
index 1b9a587..0000000
--- a/include/elf/i960.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* Intel 960 ELF support for BFD.
-   Copyright (C) 1999-2018 Free Software Foundation, Inc.
-
-   This file is part of BFD, the Binary File Descriptor library.
-
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 3 of the License, or
-   (at your option) any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; if not, write to the Free Software Foundation,
-   Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.  */
-
-#ifndef _ELF_I960_H
-#define _ELF_I960_H
-
-#include "elf/reloc-macros.h"
-
-
-START_RELOC_NUMBERS (elf_i960_reloc_type)
-     RELOC_NUMBER (R_960_NONE,	    0)
-     RELOC_NUMBER (R_960_12,	    1)
-     RELOC_NUMBER (R_960_32,	    2)
-     RELOC_NUMBER (R_960_IP24,	    3)
-     RELOC_NUMBER (R_960_SUB,	    4)
-     RELOC_NUMBER (R_960_OPTCALL,   5)
-     RELOC_NUMBER (R_960_OPTCALLX,  6)
-     RELOC_NUMBER (R_960_OPTCALLXA, 7)
-END_RELOC_NUMBERS (R_960_max)
-
-#endif /* _ELF_I960_H */
diff --git a/include/opcode/i860.h b/include/opcode/i860.h
deleted file mode 100644
index 3a0e57f..0000000
--- a/include/opcode/i860.h
+++ /dev/null
@@ -1,506 +0,0 @@
-/* Table of opcodes for the i860.
-   Copyright (C) 1989-2018 Free Software Foundation, Inc.
-
-   This file is part of the GNU opcodes library.
-
-   GAS/GDB is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 3, or (at your option)
-   any later version.
-
-   GAS/GDB is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with GAS or GDB; see the file COPYING3.  If not, write to
-   the Free Software Foundation, 51 Franklin Street - Fifth Floor,
-   Boston, MA 02110-1301, USA.  */
-
-/* Structure of an opcode table entry.  */
-struct i860_opcode
-{
-    /* The opcode name.  */
-    const char *name;
-
-    /* Bits that must be set.  */
-    unsigned long match;
-
-    /* Bits that must not be set.  */
-    unsigned long lose;
-
-    const char *args;
-
-    /* Nonzero if this is a possible expand-instruction.  */
-    char expand;
-};
-
-
-enum expand_type
-{
-    E_MOV = 1, E_ADDR, E_U32, E_AND, E_S32, E_DELAY, XP_ONLY
-};
-
-
-/* All i860 opcodes are 32 bits, except for the pseudo-instructions
-   and the operations utilizing a 32-bit address expression, an
-   unsigned 32-bit constant, or a signed 32-bit constant.
-   These opcodes are expanded into a two-instruction sequence for
-   any situation where the immediate operand does not fit in 32 bits.
-   In the case of the add and subtract operations the expansion is
-   to a three-instruction sequence (ex: orh, or, adds).  In cases
-   where the address is to be relocated, the instruction is
-   expanded to handle the worse case, this could be optimized at
-   the final link if the actual address were known.
-
-   The pseudoinstructions are:  mov, fmov, pmov, nop, and fnop.
-   These instructions are implemented as a one or two instruction
-   sequence of other operations.
-
-   The match component is a mask saying which bits must match a
-   particular opcode in order for an instruction to be an instance
-   of that opcode.
-
-   The args component is a string containing one character
-   for each operand of the instruction.
-
-Kinds of operands:
-   #    Number used by optimizer.  It is ignored.
-   1    src1 integer register.
-   2    src2 integer register.
-   d    dest register.
-   c	ctrlreg control register.
-   i    16 bit immediate.
-   I    16 bit immediate, aligned 2^0. (ld.b)
-   J    16 bit immediate, aligned 2^1. (ld.s)
-   K    16 bit immediate, aligned 2^2. (ld.l, {p}fld.l, fst.l)
-   L    16 bit immediate, aligned 2^3. ({p}fld.d, fst.d)
-   M    16 bit immediate, aligned 2^4. ({p}fld.q, fst.q)
-   5    5 bit immediate.
-   l    lbroff 26 bit PC relative immediate.
-   r    sbroff 16 bit PC relative immediate.
-   s	split 16 bit immediate.
-   S	split 16 bit immediate, aligned 2^0. (st.b)
-   T	split 16 bit immediate, aligned 2^1. (st.s)
-   U	split 16 bit immediate, aligned 2^2. (st.l)
-   e    src1 floating point register.
-   f    src2 floating point register.
-   g    dest floating point register.  */
-
-
-/* The order of the opcodes in this table is significant. The assembler
-   requires that all instances of the same mnemonic must be consecutive.
-   If they aren't, the assembler will not function properly.
- 
-   The order of opcodes does not affect the disassembler.  */
-
-static const struct i860_opcode i860_opcodes[] =
-{
-/* REG-Format Instructions.  */
-{ "ld.c",	0x30000000, 0xcc000000, "c,d", 0 },	/* ld.c csrc2,idest */
-{ "ld.b",	0x00000000, 0xfc000000, "1(2),d", 0 },	/* ld.b isrc1(isrc2),idest */
-{ "ld.b",	0x04000000, 0xf8000000, "I(2),d", E_ADDR },	/* ld.b #const(isrc2),idest */
-{ "ld.s",	0x10000000, 0xec000001, "1(2),d", 0 },	/* ld.s isrc1(isrc2),idest */
-{ "ld.s",	0x14000000, 0xe8000001, "J(2),d", E_ADDR },	/* ld.s #const(isrc2),idest */
-{ "ld.l",	0x10000001, 0xec000000, "1(2),d", 0 },	/* ld.l isrc1(isrc2),idest */
-{ "ld.l",	0x14000001, 0xe8000000, "K(2),d", E_ADDR },	/* ld.l #const(isrc2),idest */
-
-{ "st.c",	0x38000000, 0xc4000000, "1,c", 0 },	/* st.c isrc1ni,csrc2 */
-{ "st.b",	0x0c000000, 0xf0000000, "1,S(2)", E_ADDR },	/* st.b isrc1ni,#const(isrc2) */
-{ "st.s",	0x1c000000, 0xe0000001, "1,T(2)", E_ADDR },	/* st.s isrc1ni,#const(isrc2) */
-{ "st.l",	0x1c000001, 0xe0000000, "1,U(2)", E_ADDR },	/* st.l isrc1ni,#const(isrc2) */
-
-{ "ixfr",	0x08000000, 0xf4000000, "1,g", 0 },	/* ixfr isrc1ni,fdest */
-
-{ "fld.l",	0x20000002, 0xdc000001, "1(2),g", 0 },	/* fld.l isrc1(isrc2),fdest */
-{ "fld.l",	0x24000002, 0xd8000001, "K(2),g", E_ADDR },	/* fld.l #const(isrc2),fdest */
-{ "fld.l",	0x20000003, 0xdc000000, "1(2)++,g", 0 },	/* fld.l isrc1(isrc2)++,fdest */
-{ "fld.l",	0x24000003, 0xd8000000, "K(2)++,g", E_ADDR },	/* fld.l #const(isrc2)++,fdest */
-{ "fld.d",	0x20000000, 0xdc000007, "1(2),g", 0 },	/* fld.d isrc1(isrc2),fdest */
-{ "fld.d",	0x24000000, 0xd8000007, "L(2),g", E_ADDR },	/* fld.d #const(isrc2),fdest */
-{ "fld.d",	0x20000001, 0xdc000006, "1(2)++,g", 0 },	/* fld.d isrc1(isrc2)++,fdest */
-{ "fld.d",	0x24000001, 0xd8000006, "L(2)++,g", E_ADDR },	/* fld.d #const(isrc2)++,fdest */
-{ "fld.q",	0x20000004, 0xdc000003, "1(2),g", 0 },	/* fld.q isrc1(isrc2),fdest */
-{ "fld.q",	0x24000004, 0xd8000003, "M(2),g", E_ADDR },	/* fld.q #const(isrc2),fdest */
-{ "fld.q",	0x20000005, 0xdc000002, "1(2)++,g", 0 },	/* fld.q isrc1(isrc2)++,fdest */
-{ "fld.q",	0x24000005, 0xd8000002, "M(2)++,g", E_ADDR },	/* fld.q #const(isrc2)++,fdest */
-
-{ "pfld.l",	0x60000002, 0x9c000001, "1(2),g", 0 },	/* pfld.l isrc1(isrc2),fdest */
-{ "pfld.l",	0x64000002, 0x98000001, "K(2),g", E_ADDR },	/* pfld.l #const(isrc2),fdest */
-{ "pfld.l",	0x60000003, 0x9c000000, "1(2)++,g", 0 },	/* pfld.l isrc1(isrc2)++,fdest */
-{ "pfld.l",	0x64000003, 0x98000000, "K(2)++,g", E_ADDR },	/* pfld.l #const(isrc2)++,fdest */
-{ "pfld.d",	0x60000000, 0x9c000007, "1(2),g", 0 },	/* pfld.d isrc1(isrc2),fdest */
-{ "pfld.d",	0x64000000, 0x98000007, "L(2),g", E_ADDR },	/* pfld.d #const(isrc2),fdest */
-{ "pfld.d",	0x60000001, 0x9c000006, "1(2)++,g", 0 },	/* pfld.d isrc1(isrc2)++,fdest */
-{ "pfld.d",	0x64000001, 0x98000006, "L(2)++,g", E_ADDR },	/* pfld.d #const(isrc2)++,fdest */
-{ "pfld.q",	0x60000004, 0x9c000003, "1(2),g", XP_ONLY },	/* pfld.q isrc1(isrc2),fdest */
-{ "pfld.q",	0x64000004, 0x98000003, "L(2),g", XP_ONLY },	/* pfld.q #const(isrc2),fdest */
-{ "pfld.q",	0x60000005, 0x9c000002, "1(2)++,g", XP_ONLY },	/* pfld.q isrc1(isrc2)++,fdest */
-{ "pfld.q",	0x64000005, 0x98000002, "L(2)++,g", XP_ONLY },	/* pfld.q #const(isrc2)++,fdest */
-
-{ "fst.l",	0x28000002, 0xd4000001, "g,1(2)", 0 },	/* fst.l fdest,isrc1(isrc2) */
-{ "fst.l",	0x2c000002, 0xd0000001, "g,K(2)", E_ADDR },	/* fst.l fdest,#const(isrc2) */
-{ "fst.l",	0x28000003, 0xd4000000, "g,1(2)++", 0 },	/* fst.l fdest,isrc1(isrc2)++ */
-{ "fst.l",	0x2c000003, 0xd0000000, "g,K(2)++", E_ADDR },	/* fst.l fdest,#const(isrc2)++ */
-{ "fst.d",	0x28000000, 0xd4000007, "g,1(2)", 0 },	/* fst.d fdest,isrc1(isrc2) */
-{ "fst.d",	0x2c000000, 0xd0000007, "g,L(2)", E_ADDR },	/* fst.d fdest,#const(isrc2) */
-{ "fst.d",	0x28000001, 0xd4000006, "g,1(2)++", 0 },	/* fst.d fdest,isrc1(isrc2)++ */
-{ "fst.d",	0x2c000001, 0xd0000006, "g,L(2)++", E_ADDR },	/* fst.d fdest,#const(isrc2)++ */
-{ "fst.q",	0x28000004, 0xd4000003, "g,1(2)", 0 },	/* fst.d fdest,isrc1(isrc2) */
-{ "fst.q",	0x2c000004, 0xd0000003, "g,M(2)", E_ADDR },	/* fst.d fdest,#const(isrc2) */
-{ "fst.q",	0x28000005, 0xd4000002, "g,1(2)++", 0 },	/* fst.d fdest,isrc1(isrc2)++ */
-{ "fst.q",	0x2c000005, 0xd0000002, "g,M(2)++", E_ADDR },	/* fst.d fdest,#const(isrc2)++ */
-
-{ "pst.d",	0x3c000000, 0xc0000007, "g,L(2)", E_ADDR },	/* pst.d fdest,#const(isrc2) */
-{ "pst.d",	0x3c000001, 0xc0000006, "g,L(2)++", E_ADDR },	/* pst.d fdest,#const(isrc2)++ */
-
-{ "addu",	0x80000000, 0x7c000000, "1,2,d", 0 },	/* addu isrc1,isrc2,idest */
-{ "addu",	0x84000000, 0x78000000, "i,2,d", E_S32 },	/* addu #const,isrc2,idest */
-{ "adds",	0x90000000, 0x6c000000, "1,2,d", 0 },	/* adds isrc1,isrc2,idest */
-{ "adds",	0x94000000, 0x68000000, "i,2,d", E_S32 },	/* adds #const,isrc2,idest */
-{ "subu",	0x88000000, 0x74000000, "1,2,d", 0 },	/* subu isrc1,isrc2,idest */
-{ "subu",	0x8c000000, 0x70000000, "i,2,d", E_S32 },	/* subu #const,isrc2,idest */
-{ "subs",	0x98000000, 0x64000000, "1,2,d", 0 },	/* subs isrc1,isrc2,idest */
-{ "subs",	0x9c000000, 0x60000000, "i,2,d", E_S32 },	/* subs #const,isrc2,idest */
-
-{ "shl",	0xa0000000, 0x5c000000, "1,2,d", 0 },	/* shl isrc1,isrc2,idest */
-{ "shl",	0xa4000000, 0x58000000, "i,2,d", 0 },	/* shl #const,isrc2,idest */
-{ "shr",	0xa8000000, 0x54000000, "1,2,d", 0 },	/* shr isrc1,isrc2,idest */
-{ "shr",	0xac000000, 0x50000000, "i,2,d", 0 },	/* shr #const,isrc2,idest */
-{ "shrd",	0xb0000000, 0x4c000000, "1,2,d", 0 },	/* shrd isrc1,isrc2,idest */
-{ "shra",	0xb8000000, 0x44000000, "1,2,d", 0 },	/* shra isrc1,isrc2,idest */
-{ "shra",	0xbc000000, 0x40000000, "i,2,d", 0 },	/* shra #const,isrc2,idest */
-
-{ "mov",	0xa0000000, 0x5c00f800, "2,d", 0 },	/* shl r0,isrc2,idest */
-{ "mov",	0x94000000, 0x69e00000, "i,d", E_MOV },	/* adds #const,r0,idest */
-{ "nop",	0xa0000000, 0x5ffff800, "", 0 },	/* shl r0,r0,r0 */
-{ "fnop",	0xb0000000, 0x4ffff800, "", 0 },	/* shrd r0,r0,r0 */
-
-{ "trap",	0x44000000, 0xb8000000, "1,2,d", 0 },	/* trap isrc1ni,isrc2,idest */
-
-{ "flush",	0x34000004, 0xc81f0003, "L(2)", E_ADDR },	/* flush #const(isrc2) */
-{ "flush",	0x34000005, 0xc81f0002, "L(2)++", E_ADDR },	/* flush #const(isrc2)++ */
-
-{ "and",	0xc0000000, 0x3c000000, "1,2,d", 0 },	/* and isrc1,isrc2,idest */
-{ "and",	0xc4000000, 0x38000000, "i,2,d", E_AND },	/* and #const,isrc2,idest */
-{ "andh",	0xcc000000, 0x30000000, "i,2,d", 0 },	/* andh #const,isrc2,idest */
-{ "andnot",	0xd0000000, 0x2c000000, "1,2,d", 0 },	/* andnot isrc1,isrc2,idest */
-{ "andnot",	0xd4000000, 0x28000000, "i,2,d", E_U32 },	/* andnot #const,isrc2,idest */
-{ "andnoth",	0xdc000000, 0x20000000, "i,2,d", 0 },	/* andnoth #const,isrc2,idest */
-{ "or",		0xe0000000, 0x1c000000, "1,2,d", 0 },	/* or isrc1,isrc2,idest */
-{ "or",		0xe4000000, 0x18000000, "i,2,d", E_U32 },	/* or #const,isrc2,idest */
-{ "orh",	0xec000000, 0x10000000, "i,2,d", 0 },	/* orh #const,isrc2,idest */
-{ "xor",	0xf0000000, 0x0c000000, "1,2,d", 0 },	/* xor isrc1,isrc2,idest */
-{ "xor",	0xf4000000, 0x08000000, "i,2,d", E_U32 },	/* xor #const,isrc2,idest */
-{ "xorh",	0xfc000000, 0x00000000, "i,2,d", 0 },	/* xorh #const,isrc2,idest */
-
-{ "bte",	0x58000000, 0xa4000000, "1,2,r", 0 },	/* bte isrc1s,isrc2,sbroff */
-{ "bte",	0x5c000000, 0xa0000000, "5,2,r", 0 },	/* bte #const5,isrc2,sbroff */
-{ "btne",	0x50000000, 0xac000000, "1,2,r", 0 },	/* btne isrc1s,isrc2,sbroff */
-{ "btne",	0x54000000, 0xa8000000, "5,2,r", 0 },	/* btne #const5,isrc2,sbroff */
-{ "bla",	0xb4000000, 0x48000000, "1,2,r", E_DELAY },	/* bla isrc1s,isrc2,sbroff */
-{ "bri",	0x40000000, 0xbc000000, "1", E_DELAY },	/* bri isrc1ni */
-
-/* Core Escape Instruction Format */
-{ "lock",	0x4c000001, 0xb000001e, "", 0 },	/* lock set BL in dirbase */
-{ "calli",	0x4c000002, 0xb000001d, "1", E_DELAY },	/* calli isrc1ni */
-{ "intovr",	0x4c000004, 0xb000001b, "", 0 },	/* intovr trap on integer overflow */
-{ "unlock",	0x4c000007, 0xb0000018, "", 0 },	/* unlock clear BL in dirbase */
-{ "ldio.l",	0x4c000408, 0xb00003f7, "2,d", XP_ONLY },	/* ldio.l isrc2,idest */
-{ "ldio.s",	0x4c000208, 0xb00005f7, "2,d", XP_ONLY },	/* ldio.s isrc2,idest */
-{ "ldio.b",	0x4c000008, 0xb00007f7, "2,d", XP_ONLY },	/* ldio.b isrc2,idest */
-{ "stio.l",	0x4c000409, 0xb00003f6, "1,2", XP_ONLY },	/* stio.l isrc1ni,isrc2 */
-{ "stio.s",	0x4c000209, 0xb00005f6, "1,2", XP_ONLY },	/* stio.s isrc1ni,isrc2 */
-{ "stio.b",	0x4c000009, 0xb00007f6, "1,2", XP_ONLY },	/* stio.b isrc1ni,isrc2 */
-{ "ldint.l",	0x4c00040a, 0xb00003f5, "2,d", XP_ONLY },	/* ldint.l isrc2,idest */
-{ "ldint.s",	0x4c00020a, 0xb00005f5, "2,d", XP_ONLY },	/* ldint.s isrc2,idest */
-{ "ldint.b",	0x4c00000a, 0xb00007f5, "2,d", XP_ONLY },	/* ldint.b isrc2,idest */
-{ "scyc.b",	0x4c00000b, 0xb00007f4, "2", XP_ONLY },		/* scyc.b isrc2 */
-
-/* CTRL-Format Instructions */
-{ "br",		0x68000000, 0x94000000, "l", E_DELAY },	/* br lbroff */
-{ "call",	0x6c000000, 0x90000000, "l", E_DELAY },	/* call lbroff */
-{ "bc",		0x70000000, 0x8c000000, "l", 0 },	/* bc lbroff */
-{ "bc.t",	0x74000000, 0x88000000, "l", E_DELAY },	/* bc.t lbroff */
-{ "bnc",	0x78000000, 0x84000000, "l", 0 },	/* bnc lbroff */
-{ "bnc.t",	0x7c000000, 0x80000000, "l", E_DELAY },	/* bnc.t lbroff */
-
-/* Floating Point Escape Instruction Format - pfam.p fsrc1,fsrc2,fdest.  */
-{ "r2p1.ss",	0x48000400, 0xb40001ff, "e,f,g", 0 },
-{ "r2p1.sd",	0x48000480, 0xb400017f, "e,f,g", 0 },
-{ "r2p1.dd",	0x48000580, 0xb400007f, "e,f,g", 0 },
-{ "r2pt.ss",	0x48000401, 0xb40001fe, "e,f,g", 0 },
-{ "r2pt.sd",	0x48000481, 0xb400017e, "e,f,g", 0 },
-{ "r2pt.dd",	0x48000581, 0xb400007e, "e,f,g", 0 },
-{ "r2ap1.ss",	0x48000402, 0xb40001fd, "e,f,g", 0 },
-{ "r2ap1.sd",	0x48000482, 0xb400017d, "e,f,g", 0 },
-{ "r2ap1.dd",	0x48000582, 0xb400007d, "e,f,g", 0 },
-{ "r2apt.ss",	0x48000403, 0xb40001fc, "e,f,g", 0 },
-{ "r2apt.sd",	0x48000483, 0xb400017c, "e,f,g", 0 },
-{ "r2apt.dd",	0x48000583, 0xb400007c, "e,f,g", 0 },
-{ "i2p1.ss",	0x48000404, 0xb40001fb, "e,f,g", 0 },
-{ "i2p1.sd",	0x48000484, 0xb400017b, "e,f,g", 0 },
-{ "i2p1.dd",	0x48000584, 0xb400007b, "e,f,g", 0 },
-{ "i2pt.ss",	0x48000405, 0xb40001fa, "e,f,g", 0 },
-{ "i2pt.sd",	0x48000485, 0xb400017a, "e,f,g", 0 },
-{ "i2pt.dd",	0x48000585, 0xb400007a, "e,f,g", 0 },
-{ "i2ap1.ss",	0x48000406, 0xb40001f9, "e,f,g", 0 },
-{ "i2ap1.sd",	0x48000486, 0xb4000179, "e,f,g", 0 },
-{ "i2ap1.dd",	0x48000586, 0xb4000079, "e,f,g", 0 },
-{ "i2apt.ss",	0x48000407, 0xb40001f8, "e,f,g", 0 },
-{ "i2apt.sd",	0x48000487, 0xb4000178, "e,f,g", 0 },
-{ "i2apt.dd",	0x48000587, 0xb4000078, "e,f,g", 0 },
-{ "rat1p2.ss",	0x48000408, 0xb40001f7, "e,f,g", 0 },
-{ "rat1p2.sd",	0x48000488, 0xb4000177, "e,f,g", 0 },
-{ "rat1p2.dd",	0x48000588, 0xb4000077, "e,f,g", 0 },
-{ "m12apm.ss",	0x48000409, 0xb40001f6, "e,f,g", 0 },
-{ "m12apm.sd",	0x48000489, 0xb4000176, "e,f,g", 0 },
-{ "m12apm.dd",	0x48000589, 0xb4000076, "e,f,g", 0 },
-{ "ra1p2.ss",	0x4800040a, 0xb40001f5, "e,f,g", 0 },
-{ "ra1p2.sd",	0x4800048a, 0xb4000175, "e,f,g", 0 },
-{ "ra1p2.dd",	0x4800058a, 0xb4000075, "e,f,g", 0 },
-{ "m12ttpa.ss",	0x4800040b, 0xb40001f4, "e,f,g", 0 },
-{ "m12ttpa.sd",	0x4800048b, 0xb4000174, "e,f,g", 0 },
-{ "m12ttpa.dd",	0x4800058b, 0xb4000074, "e,f,g", 0 },
-{ "iat1p2.ss",	0x4800040c, 0xb40001f3, "e,f,g", 0 },
-{ "iat1p2.sd",	0x4800048c, 0xb4000173, "e,f,g", 0 },
-{ "iat1p2.dd",	0x4800058c, 0xb4000073, "e,f,g", 0 },
-{ "m12tpm.ss",	0x4800040d, 0xb40001f2, "e,f,g", 0 },
-{ "m12tpm.sd",	0x4800048d, 0xb4000172, "e,f,g", 0 },
-{ "m12tpm.dd",	0x4800058d, 0xb4000072, "e,f,g", 0 },
-{ "ia1p2.ss",	0x4800040e, 0xb40001f1, "e,f,g", 0 },
-{ "ia1p2.sd",	0x4800048e, 0xb4000171, "e,f,g", 0 },
-{ "ia1p2.dd",	0x4800058e, 0xb4000071, "e,f,g", 0 },
-{ "m12tpa.ss",	0x4800040f, 0xb40001f0, "e,f,g", 0 },
-{ "m12tpa.sd",	0x4800048f, 0xb4000170, "e,f,g", 0 },
-{ "m12tpa.dd",	0x4800058f, 0xb4000070, "e,f,g", 0 },
-
-/* Floating Point Escape Instruction Format - pfsm.p fsrc1,fsrc2,fdest.  */
-{ "r2s1.ss",	0x48000410, 0xb40001ef, "e,f,g", 0 },
-{ "r2s1.sd",	0x48000490, 0xb400016f, "e,f,g", 0 },
-{ "r2s1.dd",	0x48000590, 0xb400006f, "e,f,g", 0 },
-{ "r2st.ss",	0x48000411, 0xb40001ee, "e,f,g", 0 },
-{ "r2st.sd",	0x48000491, 0xb400016e, "e,f,g", 0 },
-{ "r2st.dd",	0x48000591, 0xb400006e, "e,f,g", 0 },
-{ "r2as1.ss",	0x48000412, 0xb40001ed, "e,f,g", 0 },
-{ "r2as1.sd",	0x48000492, 0xb400016d, "e,f,g", 0 },
-{ "r2as1.dd",	0x48000592, 0xb400006d, "e,f,g", 0 },
-{ "r2ast.ss",	0x48000413, 0xb40001ec, "e,f,g", 0 },
-{ "r2ast.sd",	0x48000493, 0xb400016c, "e,f,g", 0 },
-{ "r2ast.dd",	0x48000593, 0xb400006c, "e,f,g", 0 },
-{ "i2s1.ss",	0x48000414, 0xb40001eb, "e,f,g", 0 },
-{ "i2s1.sd",	0x48000494, 0xb400016b, "e,f,g", 0 },
-{ "i2s1.dd",	0x48000594, 0xb400006b, "e,f,g", 0 },
-{ "i2st.ss",	0x48000415, 0xb40001ea, "e,f,g", 0 },
-{ "i2st.sd",	0x48000495, 0xb400016a, "e,f,g", 0 },
-{ "i2st.dd",	0x48000595, 0xb400006a, "e,f,g", 0 },
-{ "i2as1.ss",	0x48000416, 0xb40001e9, "e,f,g", 0 },
-{ "i2as1.sd",	0x48000496, 0xb4000169, "e,f,g", 0 },
-{ "i2as1.dd",	0x48000596, 0xb4000069, "e,f,g", 0 },
-{ "i2ast.ss",	0x48000417, 0xb40001e8, "e,f,g", 0 },
-{ "i2ast.sd",	0x48000497, 0xb4000168, "e,f,g", 0 },
-{ "i2ast.dd",	0x48000597, 0xb4000068, "e,f,g", 0 },
-{ "rat1s2.ss",	0x48000418, 0xb40001e7, "e,f,g", 0 },
-{ "rat1s2.sd",	0x48000498, 0xb4000167, "e,f,g", 0 },
-{ "rat1s2.dd",	0x48000598, 0xb4000067, "e,f,g", 0 },
-{ "m12asm.ss",	0x48000419, 0xb40001e6, "e,f,g", 0 },
-{ "m12asm.sd",	0x48000499, 0xb4000166, "e,f,g", 0 },
-{ "m12asm.dd",	0x48000599, 0xb4000066, "e,f,g", 0 },
-{ "ra1s2.ss",	0x4800041a, 0xb40001e5, "e,f,g", 0 },
-{ "ra1s2.sd",	0x4800049a, 0xb4000165, "e,f,g", 0 },
-{ "ra1s2.dd",	0x4800059a, 0xb4000065, "e,f,g", 0 },
-{ "m12ttsa.ss",	0x4800041b, 0xb40001e4, "e,f,g", 0 },
-{ "m12ttsa.sd",	0x4800049b, 0xb4000164, "e,f,g", 0 },
-{ "m12ttsa.dd",	0x4800059b, 0xb4000064, "e,f,g", 0 },
-{ "iat1s2.ss",	0x4800041c, 0xb40001e3, "e,f,g", 0 },
-{ "iat1s2.sd",	0x4800049c, 0xb4000163, "e,f,g", 0 },
-{ "iat1s2.dd",	0x4800059c, 0xb4000063, "e,f,g", 0 },
-{ "m12tsm.ss",	0x4800041d, 0xb40001e2, "e,f,g", 0 },
-{ "m12tsm.sd",	0x4800049d, 0xb4000162, "e,f,g", 0 },
-{ "m12tsm.dd",	0x4800059d, 0xb4000062, "e,f,g", 0 },
-{ "ia1s2.ss",	0x4800041e, 0xb40001e1, "e,f,g", 0 },
-{ "ia1s2.sd",	0x4800049e, 0xb4000161, "e,f,g", 0 },
-{ "ia1s2.dd",	0x4800059e, 0xb4000061, "e,f,g", 0 },
-{ "m12tsa.ss",	0x4800041f, 0xb40001e0, "e,f,g", 0 },
-{ "m12tsa.sd",	0x4800049f, 0xb4000160, "e,f,g", 0 },
-{ "m12tsa.dd",	0x4800059f, 0xb4000060, "e,f,g", 0 },
-
-/* Floating Point Escape Instruction Format - pfmam.p fsrc1,fsrc2,fdest.  */
-{ "mr2p1.ss",	0x48000000, 0xb40005ff, "e,f,g", 0 },
-{ "mr2p1.sd",	0x48000080, 0xb400057f, "e,f,g", 0 },
-{ "mr2p1.dd",	0x48000180, 0xb400047f, "e,f,g", 0 },
-{ "mr2pt.ss",	0x48000001, 0xb40005fe, "e,f,g", 0 },
-{ "mr2pt.sd",	0x48000081, 0xb400057e, "e,f,g", 0 },
-{ "mr2pt.dd",	0x48000181, 0xb400047e, "e,f,g", 0 },
-{ "mr2mp1.ss",	0x48000002, 0xb40005fd, "e,f,g", 0 },
-{ "mr2mp1.sd",	0x48000082, 0xb400057d, "e,f,g", 0 },
-{ "mr2mp1.dd",	0x48000182, 0xb400047d, "e,f,g", 0 },
-{ "mr2mpt.ss",	0x48000003, 0xb40005fc, "e,f,g", 0 },
-{ "mr2mpt.sd",	0x48000083, 0xb400057c, "e,f,g", 0 },
-{ "mr2mpt.dd",	0x48000183, 0xb400047c, "e,f,g", 0 },
-{ "mi2p1.ss",	0x48000004, 0xb40005fb, "e,f,g", 0 },
-{ "mi2p1.sd",	0x48000084, 0xb400057b, "e,f,g", 0 },
-{ "mi2p1.dd",	0x48000184, 0xb400047b, "e,f,g", 0 },
-{ "mi2pt.ss",	0x48000005, 0xb40005fa, "e,f,g", 0 },
-{ "mi2pt.sd",	0x48000085, 0xb400057a, "e,f,g", 0 },
-{ "mi2pt.dd",	0x48000185, 0xb400047a, "e,f,g", 0 },
-{ "mi2mp1.ss",	0x48000006, 0xb40005f9, "e,f,g", 0 },
-{ "mi2mp1.sd",	0x48000086, 0xb4000579, "e,f,g", 0 },
-{ "mi2mp1.dd",	0x48000186, 0xb4000479, "e,f,g", 0 },
-{ "mi2mpt.ss",	0x48000007, 0xb40005f8, "e,f,g", 0 },
-{ "mi2mpt.sd",	0x48000087, 0xb4000578, "e,f,g", 0 },
-{ "mi2mpt.dd",	0x48000187, 0xb4000478, "e,f,g", 0 },
-{ "mrmt1p2.ss",	0x48000008, 0xb40005f7, "e,f,g", 0 },
-{ "mrmt1p2.sd",	0x48000088, 0xb4000577, "e,f,g", 0 },
-{ "mrmt1p2.dd",	0x48000188, 0xb4000477, "e,f,g", 0 },
-{ "mm12mpm.ss",	0x48000009, 0xb40005f6, "e,f,g", 0 },
-{ "mm12mpm.sd",	0x48000089, 0xb4000576, "e,f,g", 0 },
-{ "mm12mpm.dd",	0x48000189, 0xb4000476, "e,f,g", 0 },
-{ "mrm1p2.ss",	0x4800000a, 0xb40005f5, "e,f,g", 0 },
-{ "mrm1p2.sd",	0x4800008a, 0xb4000575, "e,f,g", 0 },
-{ "mrm1p2.dd",	0x4800018a, 0xb4000475, "e,f,g", 0 },
-{ "mm12ttpm.ss",0x4800000b, 0xb40005f4, "e,f,g", 0 },
-{ "mm12ttpm.sd",0x4800008b, 0xb4000574, "e,f,g", 0 },
-{ "mm12ttpm.dd",0x4800018b, 0xb4000474, "e,f,g", 0 },
-{ "mimt1p2.ss",	0x4800000c, 0xb40005f3, "e,f,g", 0 },
-{ "mimt1p2.sd",	0x4800008c, 0xb4000573, "e,f,g", 0 },
-{ "mimt1p2.dd",	0x4800018c, 0xb4000473, "e,f,g", 0 },
-{ "mm12tpm.ss",	0x4800000d, 0xb40005f2, "e,f,g", 0 },
-{ "mm12tpm.sd",	0x4800008d, 0xb4000572, "e,f,g", 0 },
-{ "mm12tpm.dd",	0x4800018d, 0xb4000472, "e,f,g", 0 },
-{ "mim1p2.ss",	0x4800000e, 0xb40005f1, "e,f,g", 0 },
-{ "mim1p2.sd",	0x4800008e, 0xb4000571, "e,f,g", 0 },
-{ "mim1p2.dd",	0x4800018e, 0xb4000471, "e,f,g", 0 },
-
-/* Floating Point Escape Instruction Format - pfmsm.p fsrc1,fsrc2,fdest.  */
-{ "mr2s1.ss",	0x48000010, 0xb40005ef, "e,f,g", 0 },
-{ "mr2s1.sd",	0x48000090, 0xb400056f, "e,f,g", 0 },
-{ "mr2s1.dd",	0x48000190, 0xb400046f, "e,f,g", 0 },
-{ "mr2st.ss",	0x48000011, 0xb40005ee, "e,f,g", 0 },
-{ "mr2st.sd",	0x48000091, 0xb400056e, "e,f,g", 0 },
-{ "mr2st.dd",	0x48000191, 0xb400046e, "e,f,g", 0 },
-{ "mr2ms1.ss",	0x48000012, 0xb40005ed, "e,f,g", 0 },
-{ "mr2ms1.sd",	0x48000092, 0xb400056d, "e,f,g", 0 },
-{ "mr2ms1.dd",	0x48000192, 0xb400046d, "e,f,g", 0 },
-{ "mr2mst.ss",	0x48000013, 0xb40005ec, "e,f,g", 0 },
-{ "mr2mst.sd",	0x48000093, 0xb400056c, "e,f,g", 0 },
-{ "mr2mst.dd",	0x48000193, 0xb400046c, "e,f,g", 0 },
-{ "mi2s1.ss",	0x48000014, 0xb40005eb, "e,f,g", 0 },
-{ "mi2s1.sd",	0x48000094, 0xb400056b, "e,f,g", 0 },
-{ "mi2s1.dd",	0x48000194, 0xb400046b, "e,f,g", 0 },
-{ "mi2st.ss",	0x48000015, 0xb40005ea, "e,f,g", 0 },
-{ "mi2st.sd",	0x48000095, 0xb400056a, "e,f,g", 0 },
-{ "mi2st.dd",	0x48000195, 0xb400046a, "e,f,g", 0 },
-{ "mi2ms1.ss",	0x48000016, 0xb40005e9, "e,f,g", 0 },
-{ "mi2ms1.sd",	0x48000096, 0xb4000569, "e,f,g", 0 },
-{ "mi2ms1.dd",	0x48000196, 0xb4000469, "e,f,g", 0 },
-{ "mi2mst.ss",	0x48000017, 0xb40005e8, "e,f,g", 0 },
-{ "mi2mst.sd",	0x48000097, 0xb4000568, "e,f,g", 0 },
-{ "mi2mst.dd",	0x48000197, 0xb4000468, "e,f,g", 0 },
-{ "mrmt1s2.ss",	0x48000018, 0xb40005e7, "e,f,g", 0 },
-{ "mrmt1s2.sd",	0x48000098, 0xb4000567, "e,f,g", 0 },
-{ "mrmt1s2.dd",	0x48000198, 0xb4000467, "e,f,g", 0 },
-{ "mm12msm.ss",	0x48000019, 0xb40005e6, "e,f,g", 0 },
-{ "mm12msm.sd",	0x48000099, 0xb4000566, "e,f,g", 0 },
-{ "mm12msm.dd",	0x48000199, 0xb4000466, "e,f,g", 0 },
-{ "mrm1s2.ss",	0x4800001a, 0xb40005e5, "e,f,g", 0 },
-{ "mrm1s2.sd",	0x4800009a, 0xb4000565, "e,f,g", 0 },
-{ "mrm1s2.dd",	0x4800019a, 0xb4000465, "e,f,g", 0 },
-{ "mm12ttsm.ss",0x4800001b, 0xb40005e4, "e,f,g", 0 },
-{ "mm12ttsm.sd",0x4800009b, 0xb4000564, "e,f,g", 0 },
-{ "mm12ttsm.dd",0x4800019b, 0xb4000464, "e,f,g", 0 },
-{ "mimt1s2.ss",	0x4800001c, 0xb40005e3, "e,f,g", 0 },
-{ "mimt1s2.sd",	0x4800009c, 0xb4000563, "e,f,g", 0 },
-{ "mimt1s2.dd",	0x4800019c, 0xb4000463, "e,f,g", 0 },
-{ "mm12tsm.ss",	0x4800001d, 0xb40005e2, "e,f,g", 0 },
-{ "mm12tsm.sd",	0x4800009d, 0xb4000562, "e,f,g", 0 },
-{ "mm12tsm.dd",	0x4800019d, 0xb4000462, "e,f,g", 0 },
-{ "mim1s2.ss",	0x4800001e, 0xb40005e1, "e,f,g", 0 },
-{ "mim1s2.sd",	0x4800009e, 0xb4000561, "e,f,g", 0 },
-{ "mim1s2.dd",	0x4800019e, 0xb4000461, "e,f,g", 0 },
-
-{ "fmul.ss",	0x48000020, 0xb40005df, "e,f,g", 0 },	/* fmul.p fsrc1,fsrc2,fdest */
-{ "fmul.sd",	0x480000a0, 0xb400055f, "e,f,g", 0 },	/* fmul.p fsrc1,fsrc2,fdest */
-{ "fmul.dd",	0x480001a0, 0xb400045f, "e,f,g", 0 },	/* fmul.p fsrc1,fsrc2,fdest */
-{ "pfmul.ss",	0x48000420, 0xb40001df, "e,f,g", 0 },	/* pfmul.p fsrc1,fsrc2,fdest */
-{ "pfmul.sd",	0x480004a0, 0xb400015f, "e,f,g", 0 },	/* pfmul.p fsrc1,fsrc2,fdest */
-{ "pfmul.dd",	0x480005a0, 0xb400005f, "e,f,g", 0 },	/* pfmul.p fsrc1,fsrc2,fdest */
-{ "pfmul3.dd",	0x480005a4, 0xb400005b, "e,f,g", 0 },	/* pfmul3.p fsrc1,fsrc2,fdest */
-{ "fmlow.dd",	0x480001a1, 0xb400045e, "e,f,g", 0 },	/* fmlow.dd fsrc1,fsrc2,fdest */
-{ "frcp.ss",	0x48000022, 0xb40005dd, "f,g", 0 },	/* frcp.p fsrc2,fdest */
-{ "frcp.sd",	0x480000a2, 0xb400055d, "f,g", 0 },	/* frcp.p fsrc2,fdest */
-{ "frcp.dd",	0x480001a2, 0xb400045d, "f,g", 0 },	/* frcp.p fsrc2,fdest */
-{ "frsqr.ss",	0x48000023, 0xb40005dc, "f,g", 0 },	/* frsqr.p fsrc2,fdest */
-{ "frsqr.sd",	0x480000a3, 0xb400055c, "f,g", 0 },	/* frsqr.p fsrc2,fdest */
-{ "frsqr.dd",	0x480001a3, 0xb400045c, "f,g", 0 },	/* frsqr.p fsrc2,fdest */
-{ "fadd.ss",	0x48000030, 0xb40005cf, "e,f,g", 0 },	/* fadd.p fsrc1,fsrc2,fdest */
-{ "fadd.sd",	0x480000b0, 0xb400054f, "e,f,g", 0 },	/* fadd.p fsrc1,fsrc2,fdest */
-{ "fadd.dd",	0x480001b0, 0xb400044f, "e,f,g", 0 },	/* fadd.p fsrc1,fsrc2,fdest */
-{ "pfadd.ss",	0x48000430, 0xb40001cf, "e,f,g", 0 },	/* pfadd.p fsrc1,fsrc2,fdest */
-{ "pfadd.sd",	0x480004b0, 0xb400014f, "e,f,g", 0 },	/* pfadd.p fsrc1,fsrc2,fdest */
-{ "pfadd.dd",	0x480005b0, 0xb400004f, "e,f,g", 0 },	/* pfadd.p fsrc1,fsrc2,fdest */
-{ "fsub.ss",	0x48000031, 0xb40005ce, "e,f,g", 0 },	/* fsub.p fsrc1,fsrc2,fdest */
-{ "fsub.sd",	0x480000b1, 0xb400054e, "e,f,g", 0 },	/* fsub.p fsrc1,fsrc2,fdest */
-{ "fsub.dd",	0x480001b1, 0xb400044e, "e,f,g", 0 },	/* fsub.p fsrc1,fsrc2,fdest */
-{ "pfsub.ss",	0x48000431, 0xb40001ce, "e,f,g", 0 },	/* pfsub.p fsrc1,fsrc2,fdest */
-{ "pfsub.sd",	0x480004b1, 0xb400014e, "e,f,g", 0 },	/* pfsub.p fsrc1,fsrc2,fdest */
-{ "pfsub.dd",	0x480005b1, 0xb400004e, "e,f,g", 0 },	/* pfsub.p fsrc1,fsrc2,fdest */
-{ "fix.sd",	0x480000b2, 0xb400054d, "e,g", 0 },	/* fix.p fsrc1,fdest */
-{ "fix.dd",	0x480001b2, 0xb400044d, "e,g", 0 },	/* fix.p fsrc1,fdest */
-{ "pfix.sd",	0x480004b2, 0xb400014d, "e,g", 0 },	/* pfix.p fsrc1,fdest */
-{ "pfix.dd",	0x480005b2, 0xb400004d, "e,g", 0 },	/* pfix.p fsrc1,fdest */
-{ "famov.ss",	0x48000033, 0xb40005cc, "e,g", 0 },	/* famov.p fsrc1,fdest */
-{ "famov.ds",	0x48000133, 0xb40004cc, "e,g", 0 },	/* famov.p fsrc1,fdest */
-{ "famov.sd",	0x480000b3, 0xb400054c, "e,g", 0 },	/* famov.p fsrc1,fdest */
-{ "famov.dd",	0x480001b3, 0xb400044c, "e,g", 0 },	/* famov.p fsrc1,fdest */
-{ "pfamov.ss",	0x48000433, 0xb40001cc, "e,g", 0 },	/* pfamov.p fsrc1,fdest */
-{ "pfamov.ds",	0x48000533, 0xb40000cc, "e,g", 0 },	/* pfamov.p fsrc1,fdest */
-{ "pfamov.sd",	0x480004b3, 0xb400014c, "e,g", 0 },	/* pfamov.p fsrc1,fdest */
-{ "pfamov.dd",	0x480005b3, 0xb400004c, "e,g", 0 },	/* pfamov.p fsrc1,fdest */
-/* Opcode pfgt has R bit cleared; pfle has R bit set.  */
-{ "pfgt.ss",	0x48000434, 0xb40001cb, "e,f,g", 0 },	/* pfgt.p fsrc1,fsrc2,fdest */
-{ "pfgt.dd",	0x48000534, 0xb40000cb, "e,f,g", 0 },	/* pfgt.p fsrc1,fsrc2,fdest */
-/* Opcode pfgt has R bit cleared; pfle has R bit set.  */
-{ "pfle.ss",	0x480004b4, 0xb400014b, "e,f,g", 0 },	/* pfle.p fsrc1,fsrc2,fdest */
-{ "pfle.dd",	0x480005b4, 0xb400004b, "e,f,g", 0 },	/* pfle.p fsrc1,fsrc2,fdest */
-{ "pfeq.ss",	0x48000435, 0xb40001ca, "e,f,g", 0 },	/* pfeq.p fsrc1,fsrc2,fdest */
-{ "pfeq.dd",	0x48000535, 0xb40000ca, "e,f,g", 0 },	/* pfeq.p fsrc1,fsrc2,fdest */
-{ "ftrunc.sd",	0x480000ba, 0xb4000545, "e,g", 0 },	/* ftrunc.p fsrc1,fdest */
-{ "ftrunc.dd",	0x480001ba, 0xb4000445, "e,g", 0 },	/* ftrunc.p fsrc1,fdest */
-{ "pftrunc.sd",	0x480004ba, 0xb4000145, "e,g", 0 },	/* pftrunc.p fsrc1,fdest */
-{ "pftrunc.dd",	0x480005ba, 0xb4000045, "e,g", 0 },	/* pftrunc.p fsrc1,fdest */
-{ "fxfr",	0x48000040, 0xb40005bf, "e,d", 0 },	/* fxfr fsrc1,idest */
-{ "fiadd.ss",	0x48000049, 0xb40005b6, "e,f,g", 0 },	/* fiadd.w fsrc1,fsrc2,fdest */
-{ "fiadd.dd",	0x480001c9, 0xb4000436, "e,f,g", 0 },	/* fiadd.w fsrc1,fsrc2,fdest */
-{ "pfiadd.ss",	0x48000449, 0xb40001b6, "e,f,g", 0 },	/* pfiadd.w fsrc1,fsrc2,fdest */
-{ "pfiadd.dd",	0x480005c9, 0xb4000036, "e,f,g", 0 },	/* pfiadd.w fsrc1,fsrc2,fdest */
-{ "fisub.ss",	0x4800004d, 0xb40005b2, "e,f,g", 0 },	/* fisub.w fsrc1,fsrc2,fdest */
-{ "fisub.dd",	0x480001cd, 0xb4000432, "e,f,g", 0 },	/* fisub.w fsrc1,fsrc2,fdest */
-{ "pfisub.ss",	0x4800044d, 0xb40001b2, "e,f,g", 0 },	/* pfisub.w fsrc1,fsrc2,fdest */
-{ "pfisub.dd",	0x480005cd, 0xb4000032, "e,f,g", 0 },	/* pfisub.w fsrc1,fsrc2,fdest */
-{ "fzchkl",	0x480001d7, 0xb4000428, "e,f,g", 0 },	/* fzchkl fsrc1,fsrc2,fdest */
-{ "pfzchkl",	0x480005d7, 0xb4000028, "e,f,g", 0 },	/* pfzchkl fsrc1,fsrc2,fdest */
-{ "fzchks",	0x480001df, 0xb4000420, "e,f,g", 0 },	/* fzchks fsrc1,fsrc2,fdest */
-{ "pfzchks",	0x480005df, 0xb4000020, "e,f,g", 0 },	/* pfzchks fsrc1,fsrc2,fdest */
-{ "faddp",	0x480001d0, 0xb400042f, "e,f,g", 0 },	/* faddp fsrc1,fsrc2,fdest */
-{ "pfaddp",	0x480005d0, 0xb400002f, "e,f,g", 0 },	/* pfaddp fsrc1,fsrc2,fdest */
-{ "faddz",	0x480001d1, 0xb400042e, "e,f,g", 0 },	/* faddz fsrc1,fsrc2,fdest */
-{ "pfaddz",	0x480005d1, 0xb400002e, "e,f,g", 0 },	/* pfaddz fsrc1,fsrc2,fdest */
-{ "form",	0x480001da, 0xb4000425, "e,g", 0 },	/* form fsrc1,fdest */
-{ "pform",	0x480005da, 0xb4000025, "e,g", 0 },	/* pform fsrc1,fdest */
-
-/* Floating point pseudo-instructions.  */
-{ "fmov.ss",	0x48000049, 0xb7e005b6, "e,g", 0 },	/* fiadd.ss fsrc1,f0,fdest */
-{ "fmov.dd",	0x480001c9, 0xb7e00436, "e,g", 0 },	/* fiadd.dd fsrc1,f0,fdest */
-{ "fmov.sd",	0x480000b3, 0xb400054c, "e,g", 0 },	/* famov.sd fsrc1,fdest */
-{ "fmov.ds",	0x48000133, 0xb40004cc, "e,g", 0 },	/* famov.ds fsrc1,fdest */
-{ "pfmov.ds",	0x48000533, 0xb40000cc, "e,g", 0 },	/* pfamov.ds fsrc1,fdest */
-{ "pfmov.dd",	0x480005c9, 0xb7e00036, "e,g", 0 },	/* pfiadd.dd fsrc1,f0,fdest */
-{ 0, 0, 0, 0, 0 },
-
-};
-
-#define NUMOPCODES ((sizeof i860_opcodes)/(sizeof i860_opcodes[0]))
-
-
diff --git a/include/opcode/i960.h b/include/opcode/i960.h
deleted file mode 100644
index 2c7193c..0000000
--- a/include/opcode/i960.h
+++ /dev/null
@@ -1,525 +0,0 @@
-/* Basic 80960 instruction formats.
-
-   Copyright (C) 2001-2018 Free Software Foundation, Inc.
-   
-   This program is free software; you can redistribute it and/or modify
-   it under the terms of the GNU General Public License as published by
-   the Free Software Foundation; either version 3, or (at your option)
-   any later version.
-
-   This program is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-   GNU General Public License for more details.
-
-   You should have received a copy of the GNU General Public License
-   along with this program; if not, write to the Free Software
-   Foundation, Inc., 51 Franklin Street - Fifth Floor,
-   Boston, MA 02110-1301, USA.  */
- 
-/* The 'COJ' instructions are actually COBR instructions with the 'b' in
-   the mnemonic replaced by a 'j';  they are ALWAYS "de-optimized" if
-   necessary: if the displacement will not fit in 13 bits, the assembler will
-   replace them with the corresponding compare and branch instructions.
- 
-   All of the 'MEMn' instructions are the same format; the 'n' in the name
-   indicates the default index scale factor (the size of the datum operated on).
- 
-   The FBRA formats are not actually an instruction format.  They are the
-   "convenience directives" for branching on floating-point comparisons,
-   each of which generates 2 instructions (a 'bno' and one other branch).
- 
-   The CALLJ format is not actually an instruction format.  It indicates that
-   the instruction generated (a CTRL-format 'call') should have its relocation
-   specially flagged for link-time replacement with a 'bal' or 'calls' if
-   appropriate.  */ 
-
-#define CTRL	0
-#define COBR	1
-#define COJ	2
-#define REG	3
-#define MEM1	4
-#define MEM2	5
-#define MEM4	6
-#define MEM8	7
-#define MEM12	8
-#define MEM16	9
-#define FBRA	10
-#define CALLJ	11
-
-/* Masks for the mode bits in REG format instructions */
-#define M1		0x0800
-#define M2		0x1000
-#define M3		0x2000
-
-/* Generate the 12-bit opcode for a REG format instruction by placing the 
- * high 8 bits in instruction bits 24-31, the low 4 bits in instruction bits
- * 7-10.
- */
-
-#define REG_OPC(opc)	((opc & 0xff0) << 20) | ((opc & 0xf) << 7)
-
-/* Generate a template for a REG format instruction:  place the opcode bits
- * in the appropriate fields and OR in mode bits for the operands that will not
- * be used.  I.e.,
- *		set m1=1, if src1 will not be used
- *		set m2=1, if src2 will not be used
- *		set m3=1, if dst  will not be used
- *
- * Setting the "unused" mode bits to 1 speeds up instruction execution(!).
- * The information is also useful to us because some 1-operand REG instructions
- * use the src1 field, others the dst field; and some 2-operand REG instructions
- * use src1/src2, others src1/dst.  The set mode bits enable us to distinguish.
- */
-#define R_0(opc)	( REG_OPC(opc) | M1 | M2 | M3 )	/* No operands      */
-#define R_1(opc)	( REG_OPC(opc) | M2 | M3 )	/* 1 operand: src1  */
-#define R_1D(opc)	( REG_OPC(opc) | M1 | M2 )	/* 1 operand: dst   */
-#define R_2(opc)	( REG_OPC(opc) | M3 )		/* 2 ops: src1/src2 */
-#define R_2D(opc)	( REG_OPC(opc) | M2 )		/* 2 ops: src1/dst  */
-#define R_3(opc)	( REG_OPC(opc) )		/* 3 operands       */
-
-/* DESCRIPTOR BYTES FOR REGISTER OPERANDS
- *
- * Interpret names as follows:
- *	R:   global or local register only
- *	RS:  global, local, or (if target allows) special-function register only
- *	RL:  global or local register, or integer literal
- *	RSL: global, local, or (if target allows) special-function register;
- *		or integer literal
- *	F:   global, local, or floating-point register
- *	FL:  global, local, or floating-point register; or literal (including
- *		floating point)
- *
- * A number appended to a name indicates that registers must be aligned,
- * as follows:
- *	2: register number must be multiple of 2
- *	4: register number must be multiple of 4
- */
-
-#define SFR	0x10		/* Mask for the "sfr-OK" bit */
-#define LIT	0x08		/* Mask for the "literal-OK" bit */
-#define FP	0x04		/* Mask for "floating-point-OK" bit */
-
-/* This macro ors the bits together.  Note that 'align' is a mask
- * for the low 0, 1, or 2 bits of the register number, as appropriate.
- */
-#define OP(align,lit,fp,sfr)	( align | lit | fp | sfr )
-
-#define R	OP( 0, 0,   0,  0   )
-#define RS	OP( 0, 0,   0,  SFR )
-#define RL	OP( 0, LIT, 0,  0   )
-#define RSL	OP( 0, LIT, 0,  SFR )
-#define F	OP( 0, 0,   FP, 0   )
-#define FL	OP( 0, LIT, FP, 0   )
-#define R2	OP( 1, 0,   0,  0   )
-#define RL2	OP( 1, LIT, 0,  0   )
-#define F2	OP( 1, 0,   FP, 0   )
-#define FL2	OP( 1, LIT, FP, 0   )
-#define R4	OP( 3, 0,   0,  0   )
-#define RL4	OP( 3, LIT, 0,  0   )
-#define F4	OP( 3, 0,   FP, 0   )
-#define FL4	OP( 3, LIT, FP, 0   )
-
-#define M	0x7f	/* Memory operand (MEMA & MEMB format instructions) */
-
-/* Macros to extract info from the register operand descriptor byte 'od'.
- */
-#define SFR_OK(od)	(od & SFR)	/* TRUE if sfr operand allowed */
-#define LIT_OK(od)	(od & LIT)	/* TRUE if literal operand allowed */
-#define FP_OK(od)	(od & FP)	/* TRUE if floating-point op allowed */
-#define REG_ALIGN(od,n)	((od & 0x3 & n) == 0)
-					/* TRUE if reg #n is properly aligned */
-#define MEMOP(od)	(od == M)	/* TRUE if operand is a memory operand*/
-
-/* Description of a single i80960 instruction */
-struct i960_opcode {
-	long opcode;	/* 32 bits, constant fields filled in, rest zeroed */
-	const char *name;	/* Assembler mnemonic				   */
-	short iclass;	/* Class: see #defines below			   */
-	char format;	/* REG, COBR, CTRL, MEMn, COJ, FBRA, or CALLJ	   */
-	char num_ops;	/* Number of operands				   */
-	char operand[3];/* Operand descriptors; same order as assembler instr */
-};
-
-/* Classes of 960 instructions:
- *	- each instruction falls into one class.
- *	- each target architecture supports one or more classes.
- *
- * EACH CONSTANT MUST CONTAIN 1 AND ONLY 1 SET BIT!:  see targ_has_iclass().
- */
-#define I_BASE	0x01	/* 80960 base instruction set	*/
-#define I_CX	0x02	/* 80960Cx instruction		*/
-#define I_DEC	0x04	/* Decimal instruction		*/
-#define I_FP	0x08	/* Floating point instruction	*/
-#define I_KX	0x10	/* 80960Kx instruction		*/
-#define I_MIL	0x20	/* Military instruction		*/
-#define I_CASIM	0x40	/* CA simulator instruction	*/
-#define I_CX2	0x80	/* Cx/Jx/Hx instructions	*/
-#define I_JX	0x100	/* Jx/Hx instruction		*/
-#define I_HX	0x200	/* Hx instructions		*/
-
-/******************************************************************************
- *
- *		TABLE OF i960 INSTRUCTION DESCRIPTIONS
- *
- ******************************************************************************/
-
-const struct i960_opcode i960_opcodes[] = {
-
-	/* if a CTRL instruction has an operand, it's always a displacement */
-
-	/* callj default=='call' */
-	{ 0x09000000,	"callj",	I_BASE,	CALLJ, 	1, { 0, 0, 0 } },
-	{ 0x08000000,	"b",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
-	{ 0x09000000,	"call",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
-	{ 0x0a000000,	"ret",		I_BASE,	CTRL, 	0, { 0, 0, 0 } },
-	{ 0x0b000000,	"bal",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
-	{ 0x10000000,	"bno",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
-	/* bf same as bno */
-	{ 0x10000000,	"bf",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
-	/* bru same as bno */
-	{ 0x10000000,	"bru",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
-	{ 0x11000000,	"bg",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
-	/* brg same as bg */
-	{ 0x11000000,	"brg",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
-	{ 0x12000000,	"be",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
-	/* bre same as be */
-	{ 0x12000000,	"bre",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
-	{ 0x13000000,	"bge",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
-	/* brge same as bge */
-	{ 0x13000000,	"brge",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
-	{ 0x14000000,	"bl",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
-	/* brl same as bl */
-	{ 0x14000000,	"brl",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
-	{ 0x15000000,	"bne",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
-	/* brlg same as bne */
-	{ 0x15000000,	"brlg",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
-	{ 0x16000000,	"ble",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
-	/* brle same as ble */
-	{ 0x16000000,	"brle",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
-	{ 0x17000000,	"bo",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
-	/* bt same as bo */
-	{ 0x17000000,	"bt",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
-	/* bro same as bo */
-	{ 0x17000000,	"bro",		I_BASE,	CTRL, 	1, { 0, 0, 0 } },
-	{ 0x18000000,	"faultno",	I_BASE,	CTRL, 	0, { 0, 0, 0 } },
-	/* faultf same as faultno */
-	{ 0x18000000,	"faultf",	I_BASE,	CTRL, 	0, { 0, 0, 0 } },
-	{ 0x19000000,	"faultg",	I_BASE,	CTRL, 	0, { 0, 0, 0 } },
-	{ 0x1a000000,	"faulte",	I_BASE,	CTRL, 	0, { 0, 0, 0 } },
-	{ 0x1b000000,	"faultge",	I_BASE,	CTRL, 	0, { 0, 0, 0 } },
-	{ 0x1c000000,	"faultl",	I_BASE,	CTRL, 	0, { 0, 0, 0 } },
-	{ 0x1d000000,	"faultne",	I_BASE,	CTRL, 	0, { 0, 0, 0 } },
-	{ 0x1e000000,	"faultle",	I_BASE,	CTRL, 	0, { 0, 0, 0 } },
-	{ 0x1f000000,	"faulto",	I_BASE,	CTRL, 	0, { 0, 0, 0 } },
-	/* faultt syn for faulto */
-	{ 0x1f000000,	"faultt",	I_BASE,	CTRL, 	0, { 0, 0, 0 } },
-
-	{ 0x01000000,	"syscall",	I_CASIM,CTRL, 	0, { 0, 0, 0 } },
-
-	/* If a COBR (or COJ) has 3 operands, the last one is always a
-	 * displacement and does not appear explicitly in the table.
-	 */
-
-	{ 0x20000000,	"testno",	I_BASE,	COBR,	1, { R, 0, 0 }	},
-	{ 0x21000000,	"testg",	I_BASE,	COBR,	1, { R, 0, 0 }	},
-	{ 0x22000000,	"teste",	I_BASE,	COBR,	1, { R, 0, 0 }	},
-	{ 0x23000000,	"testge",	I_BASE,	COBR,	1, { R, 0, 0 }	},
-	{ 0x24000000,	"testl",	I_BASE,	COBR,	1, { R, 0, 0 }	},
-	{ 0x25000000,	"testne",	I_BASE,	COBR,	1, { R, 0, 0 }	},
-	{ 0x26000000,	"testle",	I_BASE,	COBR,	1, { R, 0, 0 }	},
-	{ 0x27000000,	"testo",	I_BASE,	COBR,	1, { R, 0, 0 }	},
-	{ 0x30000000,	"bbc",		I_BASE,	COBR,	3, { RL, RS, 0 } },
-	{ 0x31000000,	"cmpobg",	I_BASE,	COBR,	3, { RL, RS, 0 } },
-	{ 0x32000000,	"cmpobe",	I_BASE,	COBR,	3, { RL, RS, 0 } },
-	{ 0x33000000,	"cmpobge",	I_BASE,	COBR,	3, { RL, RS, 0 } },
-	{ 0x34000000,	"cmpobl",	I_BASE,	COBR,	3, { RL, RS, 0 } },
-	{ 0x35000000,	"cmpobne",	I_BASE,	COBR,	3, { RL, RS, 0 } },
-	{ 0x36000000,	"cmpoble",	I_BASE,	COBR,	3, { RL, RS, 0 } },
-	{ 0x37000000,	"bbs",		I_BASE,	COBR,	3, { RL, RS, 0 } },
-	{ 0x38000000,	"cmpibno",	I_BASE,	COBR,	3, { RL, RS, 0 } },
-	{ 0x39000000,	"cmpibg",	I_BASE,	COBR,	3, { RL, RS, 0 } },
-	{ 0x3a000000,	"cmpibe",	I_BASE,	COBR,	3, { RL, RS, 0 } },
-	{ 0x3b000000,	"cmpibge",	I_BASE,	COBR,	3, { RL, RS, 0 } },
-	{ 0x3c000000,	"cmpibl",	I_BASE,	COBR,	3, { RL, RS, 0 } },
-	{ 0x3d000000,	"cmpibne",	I_BASE,	COBR,	3, { RL, RS, 0 } },
-	{ 0x3e000000,	"cmpible",	I_BASE,	COBR,	3, { RL, RS, 0 } },
-	{ 0x3f000000,	"cmpibo",	I_BASE,	COBR,	3, { RL, RS, 0 } },
-	{ 0x31000000,	"cmpojg",	I_BASE,	COJ,	3, { RL, RS, 0 } },
-	{ 0x32000000,	"cmpoje",	I_BASE,	COJ,	3, { RL, RS, 0 } },
-	{ 0x33000000,	"cmpojge",	I_BASE,	COJ,	3, { RL, RS, 0 } },
-	{ 0x34000000,	"cmpojl",	I_BASE,	COJ,	3, { RL, RS, 0 } },
-	{ 0x35000000,	"cmpojne",	I_BASE,	COJ,	3, { RL, RS, 0 } },
-	{ 0x36000000,	"cmpojle",	I_BASE,	COJ,	3, { RL, RS, 0 } },
-	{ 0x38000000,	"cmpijno",	I_BASE,	COJ,	3, { RL, RS, 0 } },
-	{ 0x39000000,	"cmpijg",	I_BASE,	COJ,	3, { RL, RS, 0 } },
-	{ 0x3a000000,	"cmpije",	I_BASE,	COJ,	3, { RL, RS, 0 } },
-	{ 0x3b000000,	"cmpijge",	I_BASE,	COJ,	3, { RL, RS, 0 } },
-	{ 0x3c000000,	"cmpijl",	I_BASE,	COJ,	3, { RL, RS, 0 } },
-	{ 0x3d000000,	"cmpijne",	I_BASE,	COJ,	3, { RL, RS, 0 } },
-	{ 0x3e000000,	"cmpijle",	I_BASE,	COJ,	3, { RL, RS, 0 } },
-	{ 0x3f000000,	"cmpijo",	I_BASE,	COJ,	3, { RL, RS, 0 } },
-
-	{ 0x80000000,	"ldob",		I_BASE,	MEM1,	2, { M,  R,  0 } },
-	{ 0x82000000,	"stob",		I_BASE,	MEM1,	2, { R,  M,  0 } },
-	{ 0x84000000,	"bx",		I_BASE,	MEM1,	1, { M,  0,  0 } },
-	{ 0x85000000,	"balx",		I_BASE,	MEM1,	2, { M,  R,  0 } },
-	{ 0x86000000,	"callx",	I_BASE,	MEM1,	1, { M,  0,  0 } },
-	{ 0x88000000,	"ldos",		I_BASE,	MEM2,	2, { M,  R,  0 } },
-	{ 0x8a000000,	"stos",		I_BASE,	MEM2,	2, { R,  M,  0 } },
-	{ 0x8c000000,	"lda",		I_BASE,	MEM1,	2, { M,  R,  0 } },
-	{ 0x90000000,	"ld",		I_BASE,	MEM4,	2, { M,  R,  0 } },
-	{ 0x92000000,	"st",		I_BASE,	MEM4,	2, { R,  M,  0 } },
-	{ 0x98000000,	"ldl",		I_BASE,	MEM8,	2, { M,  R2, 0 } },
-	{ 0x9a000000,	"stl",		I_BASE,	MEM8,	2, { R2, M,  0 } },
-	{ 0xa0000000,	"ldt",		I_BASE,	MEM12,	2, { M,  R4, 0 } },
-	{ 0xa2000000,	"stt",		I_BASE,	MEM12,	2, { R4, M,  0 } },
-	{ 0xb0000000,	"ldq",		I_BASE,	MEM16,	2, { M,  R4, 0 } },
-	{ 0xb2000000,	"stq",		I_BASE,	MEM16,	2, { R4, M,  0 } },
-	{ 0xc0000000,	"ldib",		I_BASE,	MEM1,	2, { M,  R,  0 } },
-	{ 0xc2000000,	"stib",		I_BASE,	MEM1,	2, { R,  M,  0 } },
-	{ 0xc8000000,	"ldis",		I_BASE,	MEM2,	2, { M,  R,  0 } },
-	{ 0xca000000,	"stis",		I_BASE,	MEM2,	2, { R,  M,  0 } },
-
-	{ R_3(0x580),	"notbit",	I_BASE,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x581),	"and",		I_BASE,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x582),	"andnot",	I_BASE,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x583),	"setbit",	I_BASE,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x584),	"notand",	I_BASE,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x586),	"xor",		I_BASE,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x587),	"or",		I_BASE,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x588),	"nor",		I_BASE,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x589),	"xnor",		I_BASE,	REG,	3, { RSL,RSL,RS } },
-	{ R_2D(0x58a),	"not",		I_BASE,	REG,	2, { RSL,RS, 0 } },
-	{ R_3(0x58b),	"ornot",	I_BASE,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x58c),	"clrbit",	I_BASE,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x58d),	"notor",	I_BASE,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x58e),	"nand",		I_BASE,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x58f),	"alterbit",	I_BASE,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x590),	"addo",		I_BASE,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x591),	"addi",		I_BASE,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x592),	"subo",		I_BASE,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x593),	"subi",		I_BASE,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x598),	"shro",		I_BASE,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x59a),	"shrdi",	I_BASE,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x59b),	"shri",		I_BASE,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x59c),	"shlo",		I_BASE,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x59d),	"rotate",	I_BASE,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x59e),	"shli",		I_BASE,	REG,	3, { RSL,RSL,RS } },
-	{ R_2(0x5a0),	"cmpo",		I_BASE,	REG,	2, { RSL,RSL, 0 } },
-	{ R_2(0x5a1),	"cmpi",		I_BASE,	REG,	2, { RSL,RSL, 0 } },
-	{ R_2(0x5a2),	"concmpo",	I_BASE,	REG,	2, { RSL,RSL, 0 } },
-	{ R_2(0x5a3),	"concmpi",	I_BASE,	REG,	2, { RSL,RSL, 0 } },
-	{ R_3(0x5a4),	"cmpinco",	I_BASE,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x5a5),	"cmpinci",	I_BASE,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x5a6),	"cmpdeco",	I_BASE,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x5a7),	"cmpdeci",	I_BASE,	REG,	3, { RSL,RSL,RS } },
-	{ R_2(0x5ac),	"scanbyte",	I_BASE,	REG,	2, { RSL,RSL, 0 } },
-	{ R_2(0x5ae),	"chkbit",	I_BASE,	REG,	2, { RSL,RSL, 0 } },
-	{ R_3(0x5b0),	"addc",		I_BASE,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x5b2),	"subc",		I_BASE,	REG,	3, { RSL,RSL,RS } },
-	{ R_2D(0x5cc),	"mov",		I_BASE,	REG,	2, { RSL,RS, 0 } },
-	{ R_2D(0x5dc),	"movl",		I_BASE,	REG,	2, { RL2,R2, 0 } },
-	{ R_2D(0x5ec),	"movt",		I_BASE,	REG,	2, { RL4,R4, 0 } },
-	{ R_2D(0x5fc),	"movq",		I_BASE,	REG,	2, { RL4,R4, 0 } },
-	{ R_3(0x610),	"atmod",	I_BASE,	REG,	3, { RS, RSL,R } },
-	{ R_3(0x612),	"atadd",	I_BASE,	REG,	3, { RS, RSL,RS } },
-	{ R_2D(0x640),	"spanbit",	I_BASE,	REG,	2, { RSL,RS, 0 } },
-	{ R_2D(0x641),	"scanbit",	I_BASE,	REG,	2, { RSL,RS, 0 } },
-	{ R_3(0x645),	"modac",	I_BASE,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x650),	"modify",	I_BASE,	REG,	3, { RSL,RSL,R } },
-	{ R_3(0x651),	"extract",	I_BASE,	REG,	3, { RSL,RSL,R } },
-	{ R_3(0x654),	"modtc",	I_BASE,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x655),	"modpc",	I_BASE,	REG,	3, { RSL,RSL,R } },
-	{ R_1(0x660),	"calls",	I_BASE,	REG,	1, { RSL, 0, 0 } },
-	{ R_0(0x66b),	"mark",		I_BASE,	REG,	0, { 0, 0, 0 }	},
-	{ R_0(0x66c),	"fmark",	I_BASE,	REG,	0, { 0, 0, 0 }	},
-	{ R_0(0x66d),	"flushreg",	I_BASE,	REG,	0, { 0, 0, 0 }	},
-	{ R_0(0x66f),	"syncf",	I_BASE,	REG,	0, { 0, 0, 0 }	},
-	{ R_3(0x670),	"emul",		I_BASE,	REG,	3, { RSL,RSL,R2 } },
-	{ R_3(0x671),	"ediv",		I_BASE,	REG,	3, { RSL,RL2,RS } },
-	{ R_2D(0x672),	"cvtadr",	I_CASIM,REG, 	2, { RL, R2, 0 } },
-	{ R_3(0x701),	"mulo",		I_BASE,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x708),	"remo",		I_BASE,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x70b),	"divo",		I_BASE,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x741),	"muli",		I_BASE,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x748),	"remi",		I_BASE,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x749),	"modi",		I_BASE,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x74b),	"divi",		I_BASE,	REG,	3, { RSL,RSL,RS } },
-
-	/* Floating-point instructions */
-
-	{ R_2D(0x674),	"cvtir",	I_FP,	REG,	2, { RL, F, 0 } },
-	{ R_2D(0x675),	"cvtilr",	I_FP,	REG,	2, { RL, F, 0 } },
-	{ R_3(0x676),	"scalerl",	I_FP,	REG,	3, { RL, FL2,F2 } },
-	{ R_3(0x677),	"scaler",	I_FP,	REG,	3, { RL, FL, F } },
-	{ R_3(0x680),	"atanr",	I_FP,	REG,	3, { FL, FL, F } },
-	{ R_3(0x681),	"logepr",	I_FP,	REG,	3, { FL, FL, F } },
-	{ R_3(0x682),	"logr",		I_FP,	REG,	3, { FL, FL, F } },
-	{ R_3(0x683),	"remr",		I_FP,	REG,	3, { FL, FL, F } },
-	{ R_2(0x684),	"cmpor",	I_FP,	REG,	2, { FL, FL, 0 } },
-	{ R_2(0x685),	"cmpr",		I_FP,	REG,	2, { FL, FL, 0 } },
-	{ R_2D(0x688),	"sqrtr",	I_FP,	REG,	2, { FL, F, 0 } },
-	{ R_2D(0x689),	"expr",		I_FP,	REG,	2, { FL, F, 0 } },
-	{ R_2D(0x68a),	"logbnr",	I_FP,	REG,	2, { FL, F, 0 } },
-	{ R_2D(0x68b),	"roundr",	I_FP,	REG,	2, { FL, F, 0 } },
-	{ R_2D(0x68c),	"sinr",		I_FP,	REG,	2, { FL, F, 0 } },
-	{ R_2D(0x68d),	"cosr",		I_FP,	REG,	2, { FL, F, 0 } },
-	{ R_2D(0x68e),	"tanr",		I_FP,	REG,	2, { FL, F, 0 } },
-	{ R_1(0x68f),	"classr",	I_FP,	REG,	1, { FL, 0, 0 }	},
-	{ R_3(0x690),	"atanrl",	I_FP,	REG,	3, { FL2,FL2,F2 } },
-	{ R_3(0x691),	"logeprl",	I_FP,	REG,	3, { FL2,FL2,F2 } },
-	{ R_3(0x692),	"logrl",	I_FP,	REG,	3, { FL2,FL2,F2 } },
-	{ R_3(0x693),	"remrl",	I_FP,	REG,	3, { FL2,FL2,F2 } },
-	{ R_2(0x694),	"cmporl",	I_FP,	REG,	2, { FL2,FL2, 0 } },
-	{ R_2(0x695),	"cmprl",	I_FP,	REG,	2, { FL2,FL2, 0 } },
-	{ R_2D(0x698),	"sqrtrl",	I_FP,	REG,	2, { FL2,F2, 0 } },
-	{ R_2D(0x699),	"exprl",	I_FP,	REG,	2, { FL2,F2, 0 } },
-	{ R_2D(0x69a),	"logbnrl",	I_FP,	REG,	2, { FL2,F2, 0 } },
-	{ R_2D(0x69b),	"roundrl",	I_FP,	REG,	2, { FL2,F2, 0 } },
-	{ R_2D(0x69c),	"sinrl",	I_FP,	REG,	2, { FL2,F2, 0 } },
-	{ R_2D(0x69d),	"cosrl",	I_FP,	REG,	2, { FL2,F2, 0 } },
-	{ R_2D(0x69e),	"tanrl",	I_FP,	REG,	2, { FL2,F2, 0 } },
-	{ R_1(0x69f),	"classrl",	I_FP,	REG,	1, { FL2, 0, 0 } },
-	{ R_2D(0x6c0),	"cvtri",	I_FP,	REG,	2, { FL, R, 0 } },
-	{ R_2D(0x6c1),	"cvtril",	I_FP,	REG,	2, { FL, R2, 0 } },
-	{ R_2D(0x6c2),	"cvtzri",	I_FP,	REG,	2, { FL, R, 0 } },
-	{ R_2D(0x6c3),	"cvtzril",	I_FP,	REG,	2, { FL, R2, 0 } },
-	{ R_2D(0x6c9),	"movr",		I_FP,	REG,	2, { FL, F, 0 } },
-	{ R_2D(0x6d9),	"movrl",	I_FP,	REG,	2, { FL2,F2, 0 } },
-	{ R_2D(0x6e1),	"movre",	I_FP,	REG,	2, { FL4,F4, 0 } },
-	{ R_3(0x6e2),	"cpysre",	I_FP,	REG,	3, { FL4,FL4,F4 } },
-	{ R_3(0x6e3),	"cpyrsre",	I_FP,	REG,	3, { FL4,FL4,F4 } },
-	{ R_3(0x78b),	"divr",		I_FP,	REG,	3, { FL, FL, F } },
-	{ R_3(0x78c),	"mulr",		I_FP,	REG,	3, { FL, FL, F } },
-	{ R_3(0x78d),	"subr",		I_FP,	REG,	3, { FL, FL, F } },
-	{ R_3(0x78f),	"addr",		I_FP,	REG,	3, { FL, FL, F } },
-	{ R_3(0x79b),	"divrl",	I_FP,	REG,	3, { FL2,FL2,F2 } },
-	{ R_3(0x79c),	"mulrl",	I_FP,	REG,	3, { FL2,FL2,F2 } },
-	{ R_3(0x79d),	"subrl",	I_FP,	REG,	3, { FL2,FL2,F2 } },
-	{ R_3(0x79f),	"addrl",	I_FP,	REG,	3, { FL2,FL2,F2 } },
-
-	/* These are the floating point branch instructions.  Each actually
-	 * generates 2 branch instructions:  the first a CTRL instruction with
-	 * the indicated opcode, and the second a 'bno'.
-	 */
-
-	{ 0x12000000,	"brue",		I_FP,	FBRA, 	1, { 0, 0, 0 }	},
-	{ 0x11000000,	"brug",		I_FP,	FBRA, 	1, { 0, 0, 0 }	},
-	{ 0x13000000,	"bruge",	I_FP,	FBRA, 	1, { 0, 0, 0 }	},
-	{ 0x14000000,	"brul",		I_FP,	FBRA, 	1, { 0, 0, 0 }	},
-	{ 0x16000000,	"brule",	I_FP,	FBRA, 	1, { 0, 0, 0 }	},
-	{ 0x15000000,	"brulg",	I_FP,	FBRA, 	1, { 0, 0, 0 }	},
-
-
-	/* Decimal instructions */
-
-	{ R_3(0x642),	"daddc",	I_DEC,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x643),	"dsubc",	I_DEC,	REG,	3, { RSL,RSL,RS } },
-	{ R_2D(0x644),	"dmovt",	I_DEC,	REG,	2, { RSL,RS, 0 } },
-
-
-	/* KX extensions */
-
-	{ R_2(0x600),	"synmov",	I_KX,	REG,	2, { R,  R, 0 } },
-	{ R_2(0x601),	"synmovl",	I_KX,	REG,	2, { R,  R, 0 } },
-	{ R_2(0x602),	"synmovq",	I_KX,	REG,	2, { R,  R, 0 } },
-	{ R_2D(0x615),	"synld",	I_KX,	REG,	2, { R,  R, 0 } },
-
-
-	/* MC extensions */
-
-	{ R_3(0x603),	"cmpstr",	I_MIL,	REG,	3, { R,  R,  RL } },
-	{ R_3(0x604),	"movqstr",	I_MIL,	REG,	3, { R,  R,  RL } },
-	{ R_3(0x605),	"movstr",	I_MIL,	REG,	3, { R,  R,  RL } },
-	{ R_2D(0x613),	"inspacc",	I_MIL,	REG,	2, { R,  R, 0 } },
-	{ R_2D(0x614),	"ldphy",	I_MIL,	REG,	2, { R,  R, 0 } },
-	{ R_3(0x617),	"fill",		I_MIL,	REG,	3, { R,  RL, RL } },
-	{ R_2D(0x646),	"condrec",	I_MIL,	REG,	2, { R,  R, 0 } },
-	{ R_2D(0x656),	"receive",	I_MIL,	REG,	2, { R,  R, 0 } },
-	{ R_3(0x662),	"send",		I_MIL,	REG,	3, { R,  RL, R } },
-	{ R_1(0x663),	"sendserv",	I_MIL,	REG,	1, { R, 0, 0 }	},
-	{ R_1(0x664),	"resumprcs",	I_MIL,	REG,	1, { R, 0, 0 }	},
-	{ R_1(0x665),	"schedprcs",	I_MIL,	REG,	1, { R, 0, 0 }	},
-	{ R_0(0x666),	"saveprcs",	I_MIL,	REG,	0, { 0, 0, 0 }	},
-	{ R_1(0x668),	"condwait",	I_MIL,	REG,	1, { R, 0, 0 }	},
-	{ R_1(0x669),	"wait",		I_MIL,	REG,	1, { R, 0, 0 }	},
-	{ R_1(0x66a),	"signal",	I_MIL,	REG,	1, { R, 0, 0 }	},
-	{ R_1D(0x673),	"ldtime",	I_MIL,	REG,	1, { R2, 0, 0 }	},
-
-
-	/* CX extensions */
-
-	{ R_3(0x5d8),	"eshro",	I_CX2,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x630),	"sdma",		I_CX,	REG,	3, { RSL,RSL,RL } },
-	{ R_3(0x631),	"udma",		I_CX,	REG,	0, { 0, 0, 0 }	},
-	{ R_3(0x659),	"sysctl",	I_CX2,	REG,	3, { RSL,RSL,RL } },
-
-
-	/* Jx extensions.  */
-	{ R_3(0x780),	"addono",	I_JX,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x790),	"addog",	I_JX,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x7a0),	"addoe",	I_JX,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x7b0),	"addoge",	I_JX,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x7c0),	"addol",	I_JX,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x7d0),	"addone",	I_JX,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x7e0),	"addole",	I_JX,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x7f0),	"addoo",	I_JX,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x781),	"addino",	I_JX,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x791),	"addig",	I_JX,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x7a1),	"addie",	I_JX,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x7b1),	"addige",	I_JX,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x7c1),	"addil",	I_JX,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x7d1),	"addine",	I_JX,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x7e1),	"addile",	I_JX,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x7f1),	"addio",	I_JX,	REG,	3, { RSL,RSL,RS } },
-
-	{ R_2D(0x5ad),	"bswap",	I_JX,	REG,	2, { RSL, RS, 0 } },
-
-	{ R_2(0x594),	"cmpob",	I_JX,	REG,	2, { RSL,RSL, 0 } },
-	{ R_2(0x595),	"cmpib",	I_JX,	REG,	2, { RSL,RSL, 0 } },
-	{ R_2(0x596),	"cmpos",	I_JX,	REG,	2, { RSL,RSL, 0 } },
-	{ R_2(0x597),	"cmpis",	I_JX,	REG,	2, { RSL,RSL, 0 } },
-
-	{ R_3(0x784),	"selno",	I_JX,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x794),	"selg",		I_JX,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x7a4),	"sele",		I_JX,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x7b4),	"selge",	I_JX,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x7c4),	"sell",		I_JX,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x7d4),	"selne",	I_JX,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x7e4),	"selle",	I_JX,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x7f4),	"selo",		I_JX,	REG,	3, { RSL,RSL,RS } },
-
-	{ R_3(0x782),	"subono",	I_JX,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x792),	"subog",	I_JX,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x7a2),	"suboe",	I_JX,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x7b2),	"suboge",	I_JX,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x7c2),	"subol",	I_JX,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x7d2),	"subone",	I_JX,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x7e2),	"subole",	I_JX,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x7f2),	"suboo",	I_JX,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x783),	"subino",	I_JX,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x793),	"subig",	I_JX,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x7a3),	"subie",	I_JX,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x7b3),	"subige",	I_JX,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x7c3),	"subil",	I_JX,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x7d3),	"subine",	I_JX,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x7e3),	"subile",	I_JX,	REG,	3, { RSL,RSL,RS } },
-	{ R_3(0x7f3),	"subio",	I_JX,	REG,	3, { RSL,RSL,RS } },
-
-	{ R_3(0x65c),	"dcctl",	I_JX,	REG,	3, { RSL,RSL,RL } },
-	{ R_3(0x65b),	"icctl",	I_JX,	REG,	3, { RSL,RSL,RS } },
-	{ R_2D(0x658),	"intctl",	I_JX,	REG,	2, { RSL, RS, 0 } },
-	{ R_0(0x5b4),	"intdis",	I_JX,	REG,	0, {   0,  0, 0 } },
-	{ R_0(0x5b5),	"inten",	I_JX,	REG,	0, {   0,  0, 0 } },
-	{ R_0(0x65d),	"halt",		I_JX,	REG,	1, { RSL,  0, 0 } },
-
-	/* Hx extensions.  */
-	{ 0xac000000,	"dcinva",	I_HX,	MEM1,	1, {   M,  0, 0 } },
-
-	/* END OF TABLE */
-
-	{ 0,		NULL,		0,	0,	0, { 0, 0, 0 }	}
-};
-
- /* end of i960-opcode.h */
author	Alan Modra <amodra@gmail.com>	2018-04-11 18:46:05 +0930
committer	Alan Modra <amodra@gmail.com>	2018-04-11 21:49:30 +0930
commit	a8eb42a8b7d48ff6bd12ac83b0e31967b4f5abf1 (patch)
tree	60b19da93f47532605aea14cc4cec88b442c43f6 /include
parent	c43b2c546be1fead208b816b59c8bdcdf9562571 (diff)
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