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| author | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:13 +0100 |
|---|---|---|
| committer | Richard Sandiford <richard.sandiford@arm.com> | 2023-03-30 11:09:13 +0100 |
| commit | e87ff6724fe32ecff11fc36a19a09ab8fbc66c13 (patch) | |
| tree | 823fcf67a24355b4f02e6455769a224a5a05a1d7 /include | |
| parent | cbd11b8818335007cf960e0cecc4dec445f80327 (diff) | |
| download | fsf-binutils-gdb-e87ff6724fe32ecff11fc36a19a09ab8fbc66c13.zip fsf-binutils-gdb-e87ff6724fe32ecff11fc36a19a09ab8fbc66c13.tar.gz fsf-binutils-gdb-e87ff6724fe32ecff11fc36a19a09ab8fbc66c13.tar.bz2 | |
aarch64: Add the SME2 ADD and SUB instructions
Add support for the SME2 ADD. SUB, FADD and FSUB instructions.
SUB and FSUB have the same form as ADD and FADD, except that
ADD also has a 2-operand accumulating form.
The 64-bit ADD/SUB instructions require FEAT_SME_I16I64 and the
64-bit FADD/FSUB instructions require FEAT_SME_F64F64.
These are the first instructions to have tied register list
operands, as opposed to tied single registers.
The parse_operands change prevents unsuffixed Z registers (width==-1)
from being treated as though they had an Advanced SIMD-style suffix
(.4s etc.). It means that:
Error: expected element type rather than vector type at operand 2 -- `add za\.s\[w8,0\],{z0-z1}'
becomes:
Error: missing type suffix at operand 2 -- `add za\.s\[w8,0\],{z0-z1}'
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/aarch64.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 69e0f83..3689fff 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -487,6 +487,7 @@ enum aarch64_opnd AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */ AARCH64_OPND_SME_Zdnx2, /* SVE vector register list from [4:1]*2. */ AARCH64_OPND_SME_Zdnx4, /* SVE vector register list from [4:2]*4. */ + AARCH64_OPND_SME_Zm, /* SVE vector register list in 4-bit Zm. */ AARCH64_OPND_SME_Zmx2, /* SVE vector register list from [20:17]*2. */ AARCH64_OPND_SME_Zmx4, /* SVE vector register list from [20:18]*4. */ AARCH64_OPND_SME_Znx2, /* SVE vector register list from [9:6]*2. */ @@ -695,6 +696,8 @@ enum aarch64_insn_class movewide, pcreladdr, ic_system, + sme_fp_sd, + sme_int_sd, sme_misc, sme_mov, sme_ldr, |