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| author | Nick Clifton <nickc@redhat.com> | 2013-03-28 09:25:11 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2013-03-28 09:25:11 +0000 |
| commit | e21e1a519694011420e3c255d6278abb0b4a209e (patch) | |
| tree | 9d336198906e6f4e52289469f0f43024232a2d73 /include | |
| parent | f95f8542c5a620ce660bf9cccfd3c38f4e62722c (diff) | |
| download | fsf-binutils-gdb-e21e1a519694011420e3c255d6278abb0b4a209e.zip fsf-binutils-gdb-e21e1a519694011420e3c255d6278abb0b4a209e.tar.gz fsf-binutils-gdb-e21e1a519694011420e3c255d6278abb0b4a209e.tar.bz2 | |
PR binutils/15068
* tic6x-opcode-table.h: Fix patterns for add, ldnw and xor.
* gas/tic6x/insns16-lsd-unit.s: Correct bit patterns for mvk, add
and xor.
* gas/tic6x/insns16-lsd-unit.d: Update expected output.
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/ChangeLog | 5 | ||||
| -rw-r--r-- | include/opcode/tic6x-opcode-table.h | 18 |
2 files changed, 14 insertions, 9 deletions
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index 9f7f157..5813878 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,6 +1,11 @@ 2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com> PR binutils/15068 + * tic6x-opcode-table.h: Fix patterns for add, ldnw and xor. + +2013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com> + + PR binutils/15068 * tic6xc-insn-formats.h (FLD): Add use of bitfield array. Add 16-bit opcodes. * tic6xc-opcode-table.h: Add 16-bit insns. diff --git a/include/opcode/tic6x-opcode-table.h b/include/opcode/tic6x-opcode-table.h index 3b7ee14..d876c56 100644 --- a/include/opcode/tic6x-opcode-table.h +++ b/include/opcode/tic6x-opcode-table.h @@ -251,15 +251,15 @@ INSN(add, d, dx2op, 1cycle, C64XP, 0, ENC5(ENC(s, fu, 0), ENC(x, xpath, 1), ENC(srcdst, reg, 0), ENC(src2, reg, 1), ENC(srcdst, reg, 2))) INSNU(add, l, lsdx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, - FIX2(FIX(op, 0x7), FIX(unit, 0x0)), + FIX2(FIX(op, 0x5), FIX(unit, 0x0)), OP3(ORREG1, OHWCST1, OWREG1), ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(srcdst, reg, 2))) INSNU(add, s, lsdx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, - FIX2(FIX(op, 0x7), FIX(unit, 0x1)), + FIX2(FIX(op, 0x5), FIX(unit, 0x1)), OP3(ORREG1, OHWCST1, OWREG1), ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(srcdst, reg, 2))) INSNU(add, d, lsdx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, - FIX2(FIX(op, 0x7), FIX(unit, 0x2)), + FIX2(FIX(op, 0x5), FIX(unit, 0x2)), OP3(ORREG1, OHWCST1, OWREG1), ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(srcdst, reg, 2))) /**/ @@ -1320,7 +1320,7 @@ INSN(lddw, d, load_store, load, C64X_AND_C67X, /* 16 bits insn */ INSN(lddw, d, dpp, load, C64XP, - TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREINCR)|TIC6X_FLAG_INSN16_B15PTR|TIC6X_FLAG_INSN16_NORS, + TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(PREINCR)|TIC6X_FLAG_INSN16_B15PTR|TIC6X_FLAG_INSN16_NORS, FIX2(FIX(op, 1), FIX(dw, 1)), OP2(ORMEMSD, OWDREGD5), ENC4(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1), @@ -1477,8 +1477,8 @@ INSN(ldnw, d, load_store, load, C64X, ENC(srcdst, reg, 1))) /* 16 bits insn */ -INSN(ldnw, d, doff4_dsz_110, store, C64XP, - TIC6X_FLAG_STORE|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE), +INSN(ldnw, d, doff4_dsz_110, load, C64XP, + TIC6X_FLAG_LOAD|TIC6X_FLAG_NO_CROSS|TIC6X_FLAG_INSN16_MEM_MODE(POSITIVE), FIX2(FIX(op, 1), FIX(sz, 1)), OP2(ORMEMSW, OWTREG5), ENC5(ENC(s, fu, 0), ENC(t, rside, 0), ENC(srcdst, reg, 1), @@ -3519,15 +3519,15 @@ INSN(xor, l, l2c, 1cycle, C64XP, 0, ENC(src2, reg, 1), ENC(dst, reg, 2))) INSNU(xor, l, lsdx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, FIX2(FIX(op, 0x7), FIX(unit, 0x0)), - OP3(ORREG1, OHWCST0, OWREG1), + OP3(ORREG1, OHWCST1, OWREG1), ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(srcdst, reg, 2))) INSNU(xor, s, lsdx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, FIX2(FIX(op, 0x7), FIX(unit, 0x1)), - OP3(ORREG1, OHWCST0, OWREG1), + OP3(ORREG1, OHWCST1, OWREG1), ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(srcdst, reg, 2))) INSNU(xor, d, lsdx1, 1cycle, C64XP, TIC6X_FLAG_NO_CROSS, FIX2(FIX(op, 0x7), FIX(unit, 0x2)), - OP3(ORREG1, OHWCST0, OWREG1), + OP3(ORREG1, OHWCST1, OWREG1), ENC3(ENC(s, fu, 0), ENC(srcdst, reg, 0), ENC(srcdst, reg, 2))) /**/ |