aarch64: rcpc3: Define address operand fields and inserter/extractors

Beyond the need to encode any registers involved in data transfer and
the address base register for load/stores, it is necessary to specify
the data register addressing mode and whether the address register is
to be pre/post-indexed, whereby loads may be post-indexed and stores
pre-indexed with write-back.

The use of a single bit to specify both the indexing mode and indexing
value requires a novel function be written to accommodate this for
address operand insertion in assembly and another for extraction in
disassembly, along with the definition of two insn fields for use with
these instructions.

This therefore defines the following functions:

  - aarch64_ins_rcpc3_addr_opt_offset
  - aarch64_ins_rcpc3_addr_offset
  - aarch64_ext_rcpc3_addr_opt_offset
  - aarch64_ext_rcpc3_addr_offset

It extends the `do_special_{encoding|decoding}' functions and defines
two rcpc3 instruction fields:

  - FLD_opc2
  - FLD_rcpc3_size

1 files changed, 4 insertions, 2 deletions

diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 3c1f522..85e28d9 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -1282,7 +1282,9 @@ extern const aarch64_opcode aarch64_opcode_table[];
 #define F_OPD_NARROW (1ULL << 33)
 /* For the instruction with size[22:23] field.  */
 #define F_OPD_SIZE (1ULL << 34)
-/* Next bit is 35.  */
+/* RCPC3 instruction has the field of 'size'.  */
+#define F_RCPC3_SIZE (1ULL << 35)
+/* Next bit is 36.  */
 
 /* Instruction constraints.  */
 /* This instruction has a predication constraint on the instruction at PC+4.  */
@@ -1350,7 +1352,7 @@ opcode_has_special_coder (const aarch64_opcode *opcode)
 {
   return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
 	  | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND
-	  | F_OPD_SIZE)) != 0;
+	  | F_OPD_SIZE | F_RCPC3_SIZE)) != 0;
 }
 
 struct aarch64_name_value_pair