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| author | Alan Modra <amodra@gmail.com> | 2018-12-06 20:51:27 +1030 |
|---|---|---|
| committer | Alan Modra <amodra@gmail.com> | 2018-12-06 23:01:03 +1030 |
| commit | bb6bf75e7a1f9aaf0283895705710f415b81b6b1 (patch) | |
| tree | 4322e262020b93bbb0cf0c940737bd9a6dd71df7 /include | |
| parent | 23ebf37881dda7fcf9dd86125705a30b6e2084ce (diff) | |
| download | fsf-binutils-gdb-bb6bf75e7a1f9aaf0283895705710f415b81b6b1.zip fsf-binutils-gdb-bb6bf75e7a1f9aaf0283895705710f415b81b6b1.tar.gz fsf-binutils-gdb-bb6bf75e7a1f9aaf0283895705710f415b81b6b1.tar.bz2 | |
PowerPC @l, @h and @ha warnings, plus VLE e_li
This patch started off just adding the warnings in tc-ppc.c about
incorrect usage of @l, @h and @ha in instructions that don't have
16-bit D-form fields. That unfortunately showed up three warnings in
ld/testsuite/ld-powerpc/vle-multiseg.s on instructions like
e_li r3, IV_table@l+0x00
which was being assembled to
8: 70 60 00 00 e_li r3,0
a: R_PPC_ADDR16_LO IV_table
The ADDR16_LO reloc is of course completely bogus on e_li, which has
a split 20-bit signed integer field in bits 0x1f7fff, the low 11 bit
in 0x7ff, the next 5 bits in 0x1f0000, and the high 4 bits in 0x7800.
Applying an ADDR16_LO reloc to the instruction potentially changes
the e_li instruction to e_add2i., e_add2is, e_cmp16i, e_mull2i,
e_cmpl16i, e_cmph16i, e_cmphl16i, e_or2i, e_and2i., e_or2is, e_lis,
e_and2is, or some invalid encodings.
Now there is a relocation that suits e_li, R_PPC_VLE_ADDR20, which was
added 2017-09-05 but I can't see code in gas to generate the
relocation. In any case, VLE_ADDR20 probably doesn't have the correct
semantics for @l since ideally you'd want an @l to pair with @h or @ha
to generate a 32-bit constant. Thus @l should only produce a 16-bit
value, I think. So we need some more relocations to handle e_li it
seems, or as I do in this patch, modify the behaviour of existing
relocations when applied to e_li instructions.
include/
* opcode/ppc.h (E_OPCODE_MASK, E_LI_MASK, E_LI_INSN): Define.
bfd/
* elf32-ppc.c (ppc_elf_howto_raw <R_PPC_VLE_ADDR20>): Correct
mask and shift value.
(ppc_elf_vle_split16): Use E_OPCODE_MASK. Handle e_li
specially.
gas/
* config/tc-ppc.c (md_assemble): Adjust relocs for VLE before
TLS tweaks. Handle e_li. Warn on unexpected operand field
for lo16/hi16/ha16 relocs.
Diffstat (limited to 'include')
| -rw-r--r-- | include/ChangeLog | 4 | ||||
| -rw-r--r-- | include/opcode/ppc.h | 5 |
2 files changed, 9 insertions, 0 deletions
diff --git a/include/ChangeLog b/include/ChangeLog index b3fd56b..3b7c66d 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,7 @@ +2018-12-06 Alan Modra <amodra@gmail.com> + + * opcode/ppc.h (E_OPCODE_MASK, E_LI_MASK, E_LI_INSN): Define. + 2018-12-06 Andrew Burgess <andrew.burgess@embecosm.com> * dis-asm.h (riscv_symbol_is_valid): Declare. diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h index 2b7f51e..c7262f1 100644 --- a/include/opcode/ppc.h +++ b/include/opcode/ppc.h @@ -476,6 +476,8 @@ ppc_optional_operand_value (const struct powerpc_operand *operand, } /* PowerPC VLE insns. */ +#define E_OPCODE_MASK 0xfc00f800 + /* Form I16L, uses 16A relocs. */ #define E_OR2I_INSN 0x7000C000 #define E_AND2I_DOT_INSN 0x7000C800 @@ -492,6 +494,9 @@ ppc_optional_operand_value (const struct powerpc_operand *operand, #define E_CMPH16I_INSN 0x7000B000 #define E_CMPHL16I_INSN 0x7000B800 +#define E_LI_INSN 0x70000000 +#define E_LI_MASK 0xfc008000 + #ifdef __cplusplus } #endif |