diff options
| author | Andrew Waterman <andrew@sifive.com> | 2017-03-22 02:09:56 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@dabbelt.com> | 2017-03-31 09:35:11 -0700 |
| commit | 858f82bf7e6531f4ad821285359c759c835f9dce (patch) | |
| tree | 6a3fa51e7ca08ced8eca7882fa255fbce059a48e /include | |
| parent | 8fa5b777488105287e56937365523d01e51c2eb3 (diff) | |
| download | fsf-binutils-gdb-858f82bf7e6531f4ad821285359c759c835f9dce.zip fsf-binutils-gdb-858f82bf7e6531f4ad821285359c759c835f9dce.tar.gz fsf-binutils-gdb-858f82bf7e6531f4ad821285359c759c835f9dce.tar.bz2 | |
RISC-V: Add physical memory protection CSRs
2017-03-27 Andrew Waterman <andrew@sifive.com>
* opcode/riscv-opc.h (CSR_PMPCFG0): New define.
(CSR_PMPCFG1): Likewise.
(CSR_PMPCFG2): Likewise.
(CSR_PMPCFG3): Likewise.
(CSR_PMPADDR0): Likewise.
(CSR_PMPADDR1): Likewise.
(CSR_PMPADDR2): Likewise.
(CSR_PMPADDR3): Likewise.
(CSR_PMPADDR4): Likewise.
(CSR_PMPADDR5): Likewise.
(CSR_PMPADDR6): Likewise.
(CSR_PMPADDR7): Likewise.
(CSR_PMPADDR8): Likewise.
(CSR_PMPADDR9): Likewise.
(CSR_PMPADDR10): Likewise.
(CSR_PMPADDR11): Likewise.
(CSR_PMPADDR12): Likewise.
(CSR_PMPADDR13): Likewise.
(CSR_PMPADDR14): Likewise.
(CSR_PMPADDR15): Likewise.
(pmpcfg0): Declare register.
(pmpcfg1): Likewise.
(pmpcfg2): Likewise.
(pmpcfg3): Likewise.
(pmpaddr0): Likewise.
(pmpaddr1): Likewise.
(pmpaddr2): Likewise.
(pmpaddr3): Likewise.
(pmpaddr4): Likewise.
(pmpaddr5): Likewise.
(pmpaddr6): Likewise.
(pmpaddr7): Likewise.
(pmpaddr8): Likewise.
(pmpaddr9): Likewise.
(pmpaddr10): Likewise.
(pmpaddr11): Likewise.
(pmpaddr12): Likewise.
(pmpaddr13): Likewise.
(pmpaddr14): Likewise.
(pmpaddr15): Likewise.
Diffstat (limited to 'include')
| -rw-r--r-- | include/ChangeLog | 43 | ||||
| -rw-r--r-- | include/opcode/riscv-opc.h | 40 |
2 files changed, 83 insertions, 0 deletions
diff --git a/include/ChangeLog b/include/ChangeLog index 7b88042..70ab0a8 100644 --- a/include/ChangeLog +++ b/include/ChangeLog @@ -1,3 +1,46 @@ +2017-03-27 Andrew Waterman <andrew@sifive.com> + + * opcode/riscv-opc.h (CSR_PMPCFG0): New define. + (CSR_PMPCFG1): Likewise. + (CSR_PMPCFG2): Likewise. + (CSR_PMPCFG3): Likewise. + (CSR_PMPADDR0): Likewise. + (CSR_PMPADDR1): Likewise. + (CSR_PMPADDR2): Likewise. + (CSR_PMPADDR3): Likewise. + (CSR_PMPADDR4): Likewise. + (CSR_PMPADDR5): Likewise. + (CSR_PMPADDR6): Likewise. + (CSR_PMPADDR7): Likewise. + (CSR_PMPADDR8): Likewise. + (CSR_PMPADDR9): Likewise. + (CSR_PMPADDR10): Likewise. + (CSR_PMPADDR11): Likewise. + (CSR_PMPADDR12): Likewise. + (CSR_PMPADDR13): Likewise. + (CSR_PMPADDR14): Likewise. + (CSR_PMPADDR15): Likewise. + (pmpcfg0): Declare register. + (pmpcfg1): Likewise. + (pmpcfg2): Likewise. + (pmpcfg3): Likewise. + (pmpaddr0): Likewise. + (pmpaddr1): Likewise. + (pmpaddr2): Likewise. + (pmpaddr3): Likewise. + (pmpaddr4): Likewise. + (pmpaddr5): Likewise. + (pmpaddr6): Likewise. + (pmpaddr7): Likewise. + (pmpaddr8): Likewise. + (pmpaddr9): Likewise. + (pmpaddr10): Likewise. + (pmpaddr11): Likewise. + (pmpaddr12): Likewise. + (pmpaddr13): Likewise. + (pmpaddr14): Likewise. + (pmpaddr15): Likewise. + 2017-03-30 Pip Cet <pipcet@gmail.com> * opcode/wasm.h: New file to support wasm32 architecture. diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 8f0f2bc..b203a6a 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -624,6 +624,26 @@ #define CSR_MCAUSE 0x342 #define CSR_MBADADDR 0x343 #define CSR_MIP 0x344 +#define CSR_PMPCFG0 0x3a0 +#define CSR_PMPCFG1 0x3a1 +#define CSR_PMPCFG2 0x3a2 +#define CSR_PMPCFG3 0x3a3 +#define CSR_PMPADDR0 0x3b0 +#define CSR_PMPADDR1 0x3b1 +#define CSR_PMPADDR2 0x3b2 +#define CSR_PMPADDR3 0x3b3 +#define CSR_PMPADDR4 0x3b4 +#define CSR_PMPADDR5 0x3b5 +#define CSR_PMPADDR6 0x3b6 +#define CSR_PMPADDR7 0x3b7 +#define CSR_PMPADDR8 0x3b8 +#define CSR_PMPADDR9 0x3b9 +#define CSR_PMPADDR10 0x3ba +#define CSR_PMPADDR11 0x3bb +#define CSR_PMPADDR12 0x3bc +#define CSR_PMPADDR13 0x3bd +#define CSR_PMPADDR14 0x3be +#define CSR_PMPADDR15 0x3bf #define CSR_TSELECT 0x7a0 #define CSR_TDATA1 0x7a1 #define CSR_TDATA2 0x7a2 @@ -1116,6 +1136,26 @@ DECLARE_CSR(mepc, CSR_MEPC) DECLARE_CSR(mcause, CSR_MCAUSE) DECLARE_CSR(mbadaddr, CSR_MBADADDR) DECLARE_CSR(mip, CSR_MIP) +DECLARE_CSR(pmpcfg0, CSR_PMPCFG0) +DECLARE_CSR(pmpcfg1, CSR_PMPCFG1) +DECLARE_CSR(pmpcfg2, CSR_PMPCFG2) +DECLARE_CSR(pmpcfg3, CSR_PMPCFG3) +DECLARE_CSR(pmpaddr0, CSR_PMPADDR0) +DECLARE_CSR(pmpaddr1, CSR_PMPADDR1) +DECLARE_CSR(pmpaddr2, CSR_PMPADDR2) +DECLARE_CSR(pmpaddr3, CSR_PMPADDR3) +DECLARE_CSR(pmpaddr4, CSR_PMPADDR4) +DECLARE_CSR(pmpaddr5, CSR_PMPADDR5) +DECLARE_CSR(pmpaddr6, CSR_PMPADDR6) +DECLARE_CSR(pmpaddr7, CSR_PMPADDR7) +DECLARE_CSR(pmpaddr8, CSR_PMPADDR8) +DECLARE_CSR(pmpaddr9, CSR_PMPADDR9) +DECLARE_CSR(pmpaddr10, CSR_PMPADDR10) +DECLARE_CSR(pmpaddr11, CSR_PMPADDR11) +DECLARE_CSR(pmpaddr12, CSR_PMPADDR12) +DECLARE_CSR(pmpaddr13, CSR_PMPADDR13) +DECLARE_CSR(pmpaddr14, CSR_PMPADDR14) +DECLARE_CSR(pmpaddr15, CSR_PMPADDR15) DECLARE_CSR(tselect, CSR_TSELECT) DECLARE_CSR(tdata1, CSR_TDATA1) DECLARE_CSR(tdata2, CSR_TDATA2) |