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| author | Jin Ma <jinma@linux.alibaba.com> | 2024-01-04 10:17:40 +0800 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2024-01-05 09:59:48 +0800 |
| commit | 6a95962e258f9ef06050f11c049771a865250c6f (patch) | |
| tree | 287f74274d39575ef8311047dbb4df2a8a783f17 /include | |
| parent | 53c4e37bb18cb8d13dbe2f595bc2ebb453673771 (diff) | |
| download | fsf-binutils-gdb-6a95962e258f9ef06050f11c049771a865250c6f.zip fsf-binutils-gdb-6a95962e258f9ef06050f11c049771a865250c6f.tar.gz fsf-binutils-gdb-6a95962e258f9ef06050f11c049771a865250c6f.tar.bz2 | |
RISC-V: T-HEAD: Fix wrong instruction encoding for th.vsetvli
Since the particularity of "th.vsetvli" was not taken into account in the
initial support patches for XTheadVector, the program operation failed
due to instruction coding errors. According to T-Head SPEC ([1]), the
"vsetvl" in the XTheadVector extension consists of SEW, LMUL and EDIV,
which is quite different from the "V" extension. Therefore, we cannot
simply reuse the processing of vsetvl in V extension.
We have set up tens of thousands of test cases to ensure that no
further encoding issues are there, and and execute all compiled test
files on real HW and make sure they don't trigger SIGILL.
Ref:
[1] https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>
gas/ChangeLog:
* config/tc-riscv.c (validate_riscv_insn): Add handling for
th.vsetvli.
(my_getThVsetvliExpression): New function.
(riscv_ip): Likewise.
* testsuite/gas/riscv/x-thead-vector.d: Likewise.
* testsuite/gas/riscv/x-thead-vector.s: Likewise.
include/ChangeLog:
* opcode/riscv.h (OP_MASK_XTHEADVLMUL): New macro.
(OP_SH_XTHEADVLMUL): Likewise.
(OP_MASK_XTHEADVSEW): Likewise.
(OP_SH_XTHEADVSEW): Likewise.
(OP_MASK_XTHEADVEDIV): Likewise.
(OP_SH_XTHEADVEDIV): Likewise.
(OP_MASK_XTHEADVTYPE_RES): Likewise.
(OP_SH_XTHEADVTYPE_RES): Likewise.
opcodes/ChangeLog:
* riscv-dis.c (print_insn_args): Likewise.
* riscv-opc.c: Likewise.
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/riscv.h | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 449cb78..adea7db 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -328,6 +328,15 @@ static inline unsigned int riscv_insn_length (insn_t insn) #define OP_MASK_VWD 0x1 #define OP_SH_VWD 26 +#define OP_MASK_XTHEADVLMUL 0x3 +#define OP_SH_XTHEADVLMUL 0 +#define OP_MASK_XTHEADVSEW 0x7 +#define OP_SH_XTHEADVSEW 2 +#define OP_MASK_XTHEADVEDIV 0x3 +#define OP_SH_XTHEADVEDIV 5 +#define OP_MASK_XTHEADVTYPE_RES 0xf +#define OP_SH_XTHEADVTYPE_RES 7 + #define NVECR 32 #define NVECM 1 @@ -595,6 +604,8 @@ extern const char * const riscv_vsew[8]; extern const char * const riscv_vlmul[8]; extern const char * const riscv_vta[2]; extern const char * const riscv_vma[2]; +extern const char * const riscv_th_vlen[4]; +extern const char * const riscv_th_vediv[4]; extern const char * const riscv_fli_symval[32]; extern const float riscv_fli_numval[32]; |