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author | Alan Modra <amodra@gmail.com> | 2022-10-13 08:46:28 +1030 |
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committer | Alan Modra <amodra@gmail.com> | 2022-10-14 22:07:18 +1030 |
commit | 61a457e5da46bad626bc3b6985a58fb5ae41842d (patch) | |
tree | d3923c9cbc7483191b42daebce20f42e2788c442 /include | |
parent | d12f8998d2d086f0a6606589e5aedb7147e6f2f1 (diff) | |
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e200 LSP support
It has bothered me for a long time that we have disabled LSP (and SPE)
tests. Also the LSP test comment indicating there is something wrong
with get_powerpc_dialect. I don't think there is. Decoding of a VLE
instruction depends on whether the processor is in VLE mode (some
processors support both VLE and standard PPC) which we flag per
section with SHF_PPC_VLE for decoding when disassembling.
Background: Some versions of powerpc e200 have "Lightweight Signal
Processing" support, examples being e200z215 and e200z425. As far as
I can tell, LSP and SPE are mutually exclusive. This seems to be
borne out by insn encoding, for example LSP "zvaddih" and SPE "evaddw"
have the same encoding. So none of the processor descriptions in
ppc_opts ought to have both PPC_OPCODE_LSP and PPC_OPCODE_SPE/2, if we
want disassembly to work. I also could not find anything to suggest
that the LSP insns are enabled only in VLE mode, which means the LSP
insns should not be in vle_opcodes.
Fix all this by moving the LSP insns to their own table, and add a new
e200z2 cpu entry with LSP support, removing LSP from -me200z4 and from
-mvle. (Yes, I know, as I said above some of the e200z4 processors
have LSP. Others have SPE. It's hard to choose good options. Think
of z2 as meaning earlier, z4 as later.) Also add -mlsp to allow
adding the LSP insn set.
include/
* opcode/ppc.h (lsp_opcodes, lsp_num_opcodes): Declare.
(LSP_OP_TO_SEG): Define.
binutils/
* doc/binutils.texi: Update ppc docs.
gas/
* config/tc-ppc.c (ppc_setup_opcodes): Add lsp opcodes to ppc_hash.
* doc/c-ppc.texi: Document e200 and lsp.
* testsuite/gas/ppc/lsp-checks.d: Assemble with -me200z2.
* testsuite/gas/ppc/lsp.d: Likewise, disassembly too.
* testsuite/gas/ppc/ppc.exp: Don't xfail lsp test.
opcodes/
* ppc-dis.c (ppc_opts): Add e200z2 and lsp. Don't set
PPC_OPCODE_LSP for e200z4 or vle.
(ppc_parse_cpu): Mutually exclude LSP and SPE.
(LSP_OPCD_SEGS): Define.
(lsp_opcd_indices): New array.
(disassemble_init_powerpc): Init lsp_opcd_indices.
(lookup_lsp): New function.
(print_insn_powerpc): Call it.
* ppc-opc.c: Include libiberty.h for ARRAY_SIZE and use throughout.
(vle_opcodes): Move LSP opcodes to..
(lsp_opcodes): ..here, and sort.
(lsp_num_opcodes): New.
Diffstat (limited to 'include')
-rw-r--r-- | include/opcode/ppc.h | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h index c5d96a2..930d13d 100644 --- a/include/opcode/ppc.h +++ b/include/opcode/ppc.h @@ -78,6 +78,8 @@ extern const struct powerpc_opcode prefix_opcodes[]; extern const unsigned int prefix_num_opcodes; extern const struct powerpc_opcode vle_opcodes[]; extern const unsigned int vle_num_opcodes; +extern const struct powerpc_opcode lsp_opcodes[]; +extern const unsigned int lsp_num_opcodes; extern const struct powerpc_opcode spe2_opcodes[]; extern const unsigned int spe2_num_opcodes; @@ -255,6 +257,9 @@ extern const unsigned int spe2_num_opcodes; /* A macro to convert a VLE opcode to a VLE opcode segment. */ #define VLE_OP_TO_SEG(i) ((i) >> 1) +/* Map LSP insn to lookup segment for disassembly. */ +#define LSP_OP_TO_SEG(i) (((i) & 0x7ff) >> 6) + /* A macro to extract the extended opcode from a SPE2 instruction. */ #define SPE2_XOP(i) ((i) & 0x7ff) |