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| author | Victor Do Nascimento <victor.donascimento@arm.com> | 2023-11-20 15:32:15 +0000 |
|---|---|---|
| committer | Victor Do Nascimento <victor.donascimento@arm.com> | 2024-01-09 10:16:40 +0000 |
| commit | 5517af829887ba3b19a3f372b6b60e8098bdfa29 (patch) | |
| tree | 920b57119a6b6b1662da63f8916550a5ba35adfe /include | |
| parent | 3521a28f10900ed893f53fcceec2f66c335cb154 (diff) | |
| download | fsf-binutils-gdb-5517af829887ba3b19a3f372b6b60e8098bdfa29.zip fsf-binutils-gdb-5517af829887ba3b19a3f372b6b60e8098bdfa29.tar.gz fsf-binutils-gdb-5517af829887ba3b19a3f372b6b60e8098bdfa29.tar.bz2 | |
aarch64: Apply narrowing of allowed immediate values for SYSP
While CRn and CRm fields in the SYSP instruction are 4-bit wide and
are thus able to accommodate values in the range 0-15, the
specifications for the SYSP instructions limit their ranges to 8-9 for
CRm and 0-7 in the case of CRn.
This led to the need to signal in some way to the operand parser that
a given operand is under special restrictions regarding its use. This
is done via the new `F_OPD_NARROW' flag, indicating a narrowing in the
range of operand values for fields in the instruction tagged with the
flag.
The flag is then used in `parse_operands' when the instruction is
assembled, but needs not be taken into consideration during
disassembly.
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/aarch64.h | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 854bb74..b81475f 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -1224,7 +1224,12 @@ extern const aarch64_opcode aarch64_opcode_table[]; to be optional, then we also implicitly specify (N+1)th operand to also be optional. */ #define F_OPD_PAIR_OPT (1ULL << 32) -/* Next bit is 33. */ +/* This instruction does not allow the full range of values that the + width of fields in the assembler instruction would theoretically + allow. This impacts the constraintts on assembly but yelds no + impact on disassembly. */ +#define F_OPD_NARROW (1ULL << 33) +/* Next bit is 34. */ /* Instruction constraints. */ /* This instruction has a predication constraint on the instruction at PC+4. */ |