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| author | Srinath Parvathaneni <srinath.parvathaneni@arm.com> | 2024-01-15 09:37:32 +0000 |
|---|---|---|
| committer | Nick Clifton <nickc@redhat.com> | 2024-01-15 11:45:41 +0000 |
| commit | 39092c7a1fb0927fbbdb40e1142de816d6f3f097 (patch) | |
| tree | 39c066e97256ea52262332db3601294caf5708b6 /include | |
| parent | 88601c2d941b004b443dc4bfdf3b93ea1983d136 (diff) | |
| download | fsf-binutils-gdb-39092c7a1fb0927fbbdb40e1142de816d6f3f097.zip fsf-binutils-gdb-39092c7a1fb0927fbbdb40e1142de816d6f3f097.tar.gz fsf-binutils-gdb-39092c7a1fb0927fbbdb40e1142de816d6f3f097.tar.bz2 | |
aarch64: Add SVE2.1 dupq, eorqv and extq instructions.
Hi,
This patch add support for SVE2.1 instruction dupq, eorqv and extq.
Regression testing for aarch64-none-elf target and found no regressions.
Ok for binutils-master?
Regards,
Srinath.
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/aarch64.h | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 1af49c4..de161db 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -727,8 +727,10 @@ enum aarch64_opnd AARCH64_OPND_SVE_Zm3_19_INDEX, /* z0-z7[0-3] in Zm3_INDEX plus bit 19. */ AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22. */ AARCH64_OPND_SVE_Zm4_11_INDEX, /* z0-z15[0-3] in Zm plus bit 11. */ + AARCH64_OPND_SVE_Zm_imm4, /* SVE vector register with 4bit index. */ AARCH64_OPND_SVE_Zm4_INDEX, /* z0-z15[0-1] in Zm, bits [20,16]. */ AARCH64_OPND_SVE_Zn, /* SVE vector register in Zn. */ + AARCH64_OPND_SVE_Zn_5_INDEX, /* Indexed SVE vector register, for DUPQ. */ AARCH64_OPND_SVE_Zn_INDEX, /* Indexed SVE vector register, for DUP. */ AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */ AARCH64_OPND_SVE_Zt, /* SVE vector register in Zt. */ @@ -1002,7 +1004,8 @@ enum aarch64_insn_class cssc, gcs, the, - sve2_urqvs + sve2_urqvs, + sve_index1, }; /* Opcode enumerators. */ |