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| author | Richard Sandiford <rdsandiford@googlemail.com> | 2013-06-26 07:04:57 +0000 |
|---|---|---|
| committer | Richard Sandiford <rdsandiford@googlemail.com> | 2013-06-26 07:04:57 +0000 |
| commit | 18870af79b2034040e6009fc2719759ca6ec75e9 (patch) | |
| tree | 699072517caa1e93c5016c970c6459a0c5dbe736 /include | |
| parent | ddacd3c8e9401081d2961a397d9db58568d10344 (diff) | |
| download | fsf-binutils-gdb-18870af79b2034040e6009fc2719759ca6ec75e9.zip fsf-binutils-gdb-18870af79b2034040e6009fc2719759ca6ec75e9.tar.gz fsf-binutils-gdb-18870af79b2034040e6009fc2719759ca6ec75e9.tar.bz2 | |
include/opcode/
* mips.h: Fix comment for "1": it is now STYPE rather than SHAMT.
Use "source" rather than "destination" for microMIPS "G".
gas/
* config/tc-mips.c (validate_mips_insn): Use STYPE rather than SHAMT.
Diffstat (limited to 'include')
| -rw-r--r-- | include/opcode/ChangeLog | 5 | ||||
| -rw-r--r-- | include/opcode/mips.h | 8 |
2 files changed, 9 insertions, 4 deletions
diff --git a/include/opcode/ChangeLog b/include/opcode/ChangeLog index 9aa75d9..b927a2c 100644 --- a/include/opcode/ChangeLog +++ b/include/opcode/ChangeLog @@ -1,3 +1,8 @@ +2013-06-26 Richard Sandiford <rdsandiford@googlemail.com> + + * mips.h: Fix comment for "1": it is now STYPE rather than SHAMT. + Use "source" rather than "destination" for microMIPS "G". + 2013-06-25 Maciej W. Rozycki <macro@codesourcery.com> * mips.h: Add M_JRADDIUSP, M_JRC and M_MOVEP anonymous enum diff --git a/include/opcode/mips.h b/include/opcode/mips.h index ec9b6ba..68cd9b6 100644 --- a/include/opcode/mips.h +++ b/include/opcode/mips.h @@ -377,7 +377,7 @@ struct mips_opcode Each of these characters corresponds to a mask field defined above. - "1" 5 bit sync type (OP_*_SHAMT) + "1" 5 bit sync type (OP_*_STYPE) "<" 5 bit shift amount (OP_*_SHAMT) ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT) "a" 26 bit target address (OP_*_TARGET) @@ -1742,7 +1742,7 @@ extern const int bfd_mips16_num_opcodes; others too). "." 10-bit signed offset/number (MICROMIPSOP_*_OFFSET10) - "1" 5-bit sync type (MICROMIPSOP_*_SHAMT) + "1" 5-bit sync type (MICROMIPSOP_*_STYPE) "<" 5-bit shift amount (MICROMIPSOP_*_SHAMT) ">" shift amount between 32 and 63, stored after subtracting 32 (MICROMIPSOP_*_SHAMT) @@ -1814,9 +1814,9 @@ extern const int bfd_mips16_num_opcodes; Coprocessor instructions: "E" 5-bit target register (MICROMIPSOP_*_RT) - "G" 5-bit destination register (MICROMIPSOP_*_RS) + "G" 5-bit source register (MICROMIPSOP_*_RS) "H" 3-bit sel field for (D)MTC* and (D)MFC* (MICROMIPSOP_*_SEL) - "+D" combined destination register ("G") and sel ("H") for CP0 ops, + "+D" combined source register ("G") and sel ("H") for CP0 ops, for pretty-printing in disassembly only Macro instructions: |