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authorPeter Bergner <bergner@vnet.ibm.com>2017-12-01 11:20:15 -0600
committerPeter Bergner <bergner@vnet.ibm.com>2017-12-01 11:20:15 -0600
commit0f873fd58b51a2906f31bb445ab685da04a1be23 (patch)
treeea1f9373897a2511e08a4b82e902c4148f9afd9d /include
parentd0df06af9b70c5a6a2aa496437364f219e669067 (diff)
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Use consistent types for holding instructions, instruction masks, etc.
include/ * opcode/ppc.h (PPC_INT_FMT): Define. (struct powerpc_opcode) <opcode>: Update type. (struct powerpc_opcode) <mask>: Likewise. (struct powerpc_opcode) <bitm>: Likewise. (struct powerpc_opcode) <insert>: Likewise. (struct powerpc_opcode) <extract>: Likewise. (ppc_optional_operand_value): Likewise. gas/ * config/tc-ppc.c (last_insn): Update type. (insn_validate) <omask, mask>: Likewise. (ppc_setup_opcodes) <mask, right_bit>: Likewise. <PRINT_OPCODE_TABLE>: Update types and printf format specifiers. (ppc_insert_operand): Update return and argument types and remove unneeded type casts. <min, max, right, tmp>: Update type. (md_assemble): Remove unneeded type casts. <insn, val, tmp_insn>: Update type. opcodes/ * opcodes/ppc-dis.c (disassemble_init_powerpc): Fix white space. (operand_value_powerpc): Update return and argument type. <value, top>: Update type. (skip_optional_operands): Update argument type. (lookup_powerpc): Likewise. (lookup_vle): Likewise. <table_opcd, table_mask, insn2>: Update type. (lookup_spe2): Update argument type. <table_opcd, table_mask, insn2>: Update type. (print_insn_powerpc) <insn, value>: Update type. Use PPC_INT_FMT for printing instructions and operands. * opcodes/ppc-opc.c (insert_arx, extract_arx, insert_ary, extract_ary, insert_rx, extract_rx, insert_ry, extract_ry, insert_bat, extract_bat, insert_bba, extract_bba, insert_bdm, extract_bdm, insert_bdp, extract_bdp, valid_bo_pre_v2, valid_bo_post_v2, valid_bo, insert_bo, extract_bo, insert_boe, extract_boe, insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd, insert_dxdn, extract_dxdn, insert_fxm, extract_fxm, insert_li20, extract_li20, insert_ls, extract_ls, insert_esync, extract_esync, insert_mbe, extract_mbe, insert_mb6, extract_mb6, extract_nb, insert_nbi, insert_nsi, extract_nsi, insert_ral, extract_ral, insert_ram, extract_ram, insert_raq, extract_raq, insert_ras, extract_ras, insert_rbs, extract_rbs, insert_rbx, extract_rbx, insert_sci8, extract_sci8, insert_sci8n, extract_sci8n, insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w, insert_oimm, extract_oimm, insert_sh6, extract_sh6, insert_spr, extract_spr, insert_sprg, extract_sprg, insert_tbr, extract_tbr, insert_xt6, extract_xt6, insert_xtq6, extract_xtq6, insert_xa6, extract_xa6, insert_xb6, extract_xb6, insert_xb6s, extract_xb6s, insert_xc6, extract_xc6, insert_dm, extract_dm, insert_vlesi, extract_vlesi, insert_vlensi, extract_vlensi, insert_vleui, extract_vleui, insert_vleil, extract_vleil, insert_evuimm1_ex0, extract_evuimm1_ex0, insert_evuimm2_ex0, extract_evuimm2_ex0, insert_evuimm4_ex0, extract_evuimm4_ex0, insert_evuimm8_ex0, extract_evuimm8_ex0, insert_evuimm_lt8, extract_evuimm_lt8, insert_evuimm_lt16, extract_evuimm_lt16, insert_rD_rS_even, extract_rD_rS_even, insert_off_lsp, extract_off_lsp, insert_off_spe2, extract_off_spe2, insert_Ddd, extract_Ddd): Update types. (OP, OPTO, OPL, OPVUP, OPVUPRT, A, AFRALFRC_MASK, B, BD8, BD8IO, BD15, BD24, BBO, Y_MASK , AT1_MASK, AT2_MASK, BBOCB, C_LK, C, CTX, UCTX, DX, EVSEL, IA16, I16A, I16L, IM7, LI20, MME, MD, MDS, SC, SC_MASK, SCI8, SCI8BF, SD4, SE_IM5, SE_R, SE_RR, VX, VX_LSP, VX_RA_CONST, VX_RB_CONST, VX_SPE_CRFD, VX_SPE2_CLR, VX_SPE2_SPLATB, VX_SPE2_OCTET, VX_SPE2_DDHH, VX_SPE2_HH, VX_SPE2_EVMAR, VX_SPE2_EVMAR_MASK, VXA, VXR, VXASH, X, EX, XX2, XX3, XX3RC, XX4, Z, XWRA_MASK, XLRT_MASK, XRLARB_MASK, XLRAND_MASK, XRTLRA_MASK, XRTLRARB_MASK, XRTARARB_MASK, XRTBFRARB_MASK, XOPL, XOPL2, XRCL, XRT, XRTRA, XCMP_MASK, XCMPL_MASK, XTO, XTLB, XSYNC, XEH_MASK, XDSS, XFL, XISEL, XL, XLO, XLYLK, XLOCB, XMBAR, XO, XOPS, XS, XFXM, XSPR, XUC, XW, APU): Update types in casts.
Diffstat (limited to 'include')
-rw-r--r--include/ChangeLog10
-rw-r--r--include/opcode/ppc.h22
2 files changed, 25 insertions, 7 deletions
diff --git a/include/ChangeLog b/include/ChangeLog
index a766867..ef1cfe0 100644
--- a/include/ChangeLog
+++ b/include/ChangeLog
@@ -1,3 +1,13 @@
+2017-12-01 Peter Bergner <bergner@vnet.ibm.com>
+
+ * opcode/ppc.h (PPC_INT_FMT): Define.
+ (struct powerpc_opcode) <opcode>: Update type.
+ (struct powerpc_opcode) <mask>: Likewise.
+ (struct powerpc_opcode) <bitm>: Likewise.
+ (struct powerpc_opcode) <insert>: Likewise.
+ (struct powerpc_opcode) <extract>: Likewise.
+ (ppc_optional_operand_value): Likewise.
+
2017-11-24 H.J. Lu <hongjiu.lu@intel.com>
PR binutils/22444
diff --git a/include/opcode/ppc.h b/include/opcode/ppc.h
index a8274e1..8762cf8 100644
--- a/include/opcode/ppc.h
+++ b/include/opcode/ppc.h
@@ -30,6 +30,14 @@ extern "C" {
typedef uint64_t ppc_cpu_t;
+#if BFD_HOST_64BIT_LONG
+# define PPC_INT_FMT "l"
+#elif defined (__MSVCRT__)
+# define PPC_INT_FMT "I64"
+#else
+# define PPC_INT_FMT "ll"
+#endif
+
/* The opcode table is an array of struct powerpc_opcode. */
struct powerpc_opcode
@@ -39,13 +47,13 @@ struct powerpc_opcode
/* The opcode itself. Those bits which will be filled in with
operands are zeroes. */
- unsigned long opcode;
+ uint64_t opcode;
/* The opcode mask. This is used by the disassembler. This is a
mask containing ones indicating those bits which must match the
opcode field, and zeroes indicating those bits which need not
match (and are presumably filled in by operands). */
- unsigned long mask;
+ uint64_t mask;
/* One bit flags for the opcode. These are used to indicate which
specific processors support the instructions. The defined values
@@ -249,7 +257,7 @@ extern const int spe2_num_opcodes;
struct powerpc_operand
{
/* A bitmask of bits in the operand. */
- unsigned int bitm;
+ uint64_t bitm;
/* The shift operation to be applied to the operand. No shift
is made if this is zero. For positive values, the operand
@@ -277,8 +285,8 @@ struct powerpc_operand
string (the operand will be inserted in any case). If the
operand value is legal, *ERRMSG will be unchanged (most operands
can accept any value). */
- unsigned long (*insert)
- (unsigned long instruction, long op, ppc_cpu_t dialect, const char **errmsg);
+ uint64_t (*insert)
+ (uint64_t instruction, int64_t op, ppc_cpu_t dialect, const char **errmsg);
/* Extraction function. This is used by the disassembler. To
extract this operand type from an instruction, check this field.
@@ -299,7 +307,7 @@ struct powerpc_operand
non-zero if this operand type can not actually be extracted from
this operand (i.e., the instruction does not match). If the
operand is valid, *INVALID will not be changed. */
- long (*extract) (unsigned long instruction, ppc_cpu_t dialect, int *invalid);
+ int64_t (*extract) (uint64_t instruction, ppc_cpu_t dialect, int *invalid);
/* One bit syntax flags. */
unsigned long flags;
@@ -463,7 +471,7 @@ extern const int powerpc_num_macros;
extern ppc_cpu_t ppc_parse_cpu (ppc_cpu_t, ppc_cpu_t *, const char *);
-static inline long
+static inline int64_t
ppc_optional_operand_value (const struct powerpc_operand *operand)
{
if ((operand->flags & PPC_OPERAND_OPTIONAL_VALUE) != 0)