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| author | Christoph Müllner <christoph.muellner@vrull.eu> | 2023-11-23 01:04:47 +0100 |
|---|---|---|
| committer | Christoph Müllner <christoph.muellner@vrull.eu> | 2023-12-01 01:48:27 +0100 |
| commit | ea1bd007428cb20df9a36a049d3a0ccd9ae74894 (patch) | |
| tree | 1689f41eeb795a67ed07cbed0a5c7db842413582 /include/opcode | |
| parent | 3281156164aec0b8e547503569c64081f5f69717 (diff) | |
| download | fsf-binutils-gdb-ea1bd007428cb20df9a36a049d3a0ccd9ae74894.zip fsf-binutils-gdb-ea1bd007428cb20df9a36a049d3a0ccd9ae74894.tar.gz fsf-binutils-gdb-ea1bd007428cb20df9a36a049d3a0ccd9ae74894.tar.bz2 | |
RISC-V: Zv*: Add support for Zvkb ISA extension
Back then when the support for the RISC-V vector crypto extensions
was merged, the specification was frozen, but not ratified.
A frozen specification is allowed to change within tight bounds
before ratification and this has happend with the vector crypto
extensions.
The following changes were applied:
* A new extension Zvkb was defined, which is a strict subset of Zvbb.
* Zvkn and Zvks include now Zvkb instead of Zvbb.
This patch implements these changes between the frozen and the
ratified specification.
Note, that this technically an incompatible change of Zvkn and Zvks,
but I am not aware of any project that depends on the currently
implemented behaviour of Zvkn and Zvks. So this patch should be fine.
Reported-By: Jerry Shih <jerry.shih@sifive.com>
Reported-By: Eric Biggers <ebiggers@kernel.org>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Diffstat (limited to 'include/opcode')
| -rw-r--r-- | include/opcode/riscv-opc.h | 4 | ||||
| -rw-r--r-- | include/opcode/riscv.h | 1 |
2 files changed, 3 insertions, 2 deletions
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 1e41721..1af8475 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2121,7 +2121,7 @@ #define MASK_VDOTUVV 0xfc00707f #define MATCH_VFDOTVV 0xe4001057 #define MASK_VFDOTVV 0xfc00707f -/* Zvbb instructions. */ +/* Zvbb/Zvkb instructions. */ #define MATCH_VANDN_VV 0x4000057 #define MASK_VANDN_VV 0xfc00707f #define MATCH_VANDN_VX 0x4004057 @@ -3798,7 +3798,7 @@ DECLARE_INSN(c_ntl_all, MATCH_C_NTL_ALL, MASK_C_NTL_ALL) /* Zawrs instructions. */ DECLARE_INSN(wrs_nto, MATCH_WRS_NTO, MASK_WRS_NTO) DECLARE_INSN(wrs_sto, MATCH_WRS_STO, MASK_WRS_STO) -/* Zvbb instructions. */ +/* Zvbb/Zvkb instructions. */ DECLARE_INSN(vandn_vv, MATCH_VANDN_VV, MASK_VANDN_VV) DECLARE_INSN(vandn_vx, MATCH_VANDN_VX, MASK_VANDN_VX) DECLARE_INSN(vbrev8_v, MATCH_VBREV8_V, MASK_VBREV8_V) diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 2548686..132d686 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -439,6 +439,7 @@ enum riscv_insn_class INSN_CLASS_ZVEF, INSN_CLASS_ZVBB, INSN_CLASS_ZVBC, + INSN_CLASS_ZVKB, INSN_CLASS_ZVKG, INSN_CLASS_ZVKNED, INSN_CLASS_ZVKNHA_OR_ZVKNHB, |