RISC-V: Add vector permutation instructions for T-Head VECTOR vendor extension

T-Head has a range of vendor-specific instructions. Therefore
it makes sense to group them into smaller chunks in form of
vendor extensions.

This patch adds permutation instructions for the "XTheadVector"
extension. The 'th' prefix and the "XTheadVector" extension
are documented in a PR for the RISC-V toolchain conventions ([1]).

[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>

gas/ChangeLog:

	* testsuite/gas/riscv/x-thead-vector.d: Add tests for
	permutation instructions.
	* testsuite/gas/riscv/x-thead-vector.s: Likewise.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_TH_VMVXS): New.

opcodes/ChangeLog:

	* riscv-opc.c: Likewise.

1 files changed, 10 insertions, 0 deletions

diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 9b4288c..1e41721 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2959,6 +2959,16 @@
 #define MASK_TH_VIOTAM 0xfc0ff07f
 #define MATCH_TH_VIDV 0x5808a057
 #define MASK_TH_VIDV 0xfdfff07f
+#define MATCH_TH_VMVXS 0x32002057
+#define MASK_TH_VMVXS 0xfe0ff07f
+#define MATCH_TH_VEXTXV 0x32002057
+#define MASK_TH_VEXTXV 0xfe00707f
+#define MATCH_TH_VMVSX 0x36006057
+#define MASK_TH_VMVSX 0xfff0707f
+#define MATCH_TH_VFMVFS 0x32001057
+#define MASK_TH_VFMVFS 0xfe0ff07f
+#define MATCH_TH_VFMVSF 0x36005057
+#define MASK_TH_VFMVSF 0xfff0707f
 /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
 #define MATCH_VT_MASKC 0x607b
 #define MASK_VT_MASKC 0xfe00707f