RISC-V: Add load/store segment instructions for T-Head VECTOR vendor extension

T-Head has a range of vendor-specific instructions. Therefore it
makes sense to group them into smaller chunks in form of vendor
extensions.

This patch adds provides load/store segment instructions for T-Head VECTOR
vendor extension, which same as the "Zvlsseg" extension in RVI 0.71 vector
extension, but belongs to the "XTheadVector" extension. The 'th' prefix
and the "XTheadVector" extension are documented in a PR for the
RISC-V toolchain conventions ([1]).

[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>

gas/ChangeLog:

	* testsuite/gas/riscv/x-thead-vector.d: Add test.
	* testsuite/gas/riscv/x-thead-vector.s: Likewise.

include/ChangeLog:

	* opcode/riscv-opc.h (MATCH_TH_VLSEG2BV): New.

opcodes/ChangeLog:

	* riscv-opc.c: Likewise.

1 files changed, 169 insertions, 0 deletions

diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 792958b..6556de2 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2681,6 +2681,175 @@
 #define MASK_TH_VLHFFV   0xfdf0707f
 #define MATCH_TH_VLWFFV  0x11006007
 #define MASK_TH_VLWFFV   0xfdf0707f
+#define MATCH_TH_VLSEG2BV 0x30000007
+#define MASK_TH_VLSEG2BV 0xfdf0707f
+#define MATCH_TH_VLSEG2HV 0x30005007
+#define MASK_TH_VLSEG2HV 0xfdf0707f
+#define MATCH_TH_VLSEG2WV 0x30006007
+#define MASK_TH_VLSEG2WV 0xfdf0707f
+#define MATCH_TH_VLSEG3BV 0x50000007
+#define MASK_TH_VLSEG3BV 0xfdf0707f
+#define MATCH_TH_VLSEG3HV 0x50005007
+#define MASK_TH_VLSEG3HV 0xfdf0707f
+#define MATCH_TH_VLSEG3WV 0x50006007
+#define MASK_TH_VLSEG3WV 0xfdf0707f
+#define MATCH_TH_VLSEG4BV 0x70000007
+#define MASK_TH_VLSEG4BV 0xfdf0707f
+#define MATCH_TH_VLSEG4HV 0x70005007
+#define MASK_TH_VLSEG4HV 0xfdf0707f
+#define MATCH_TH_VLSEG4WV 0x70006007
+#define MASK_TH_VLSEG4WV 0xfdf0707f
+#define MATCH_TH_VLSEG5BV 0x90000007
+#define MASK_TH_VLSEG5BV 0xfdf0707f
+#define MATCH_TH_VLSEG5HV 0x90005007
+#define MASK_TH_VLSEG5HV 0xfdf0707f
+#define MATCH_TH_VLSEG5WV 0x90006007
+#define MASK_TH_VLSEG5WV 0xfdf0707f
+#define MATCH_TH_VLSEG6BV 0xb0000007
+#define MASK_TH_VLSEG6BV 0xfdf0707f
+#define MATCH_TH_VLSEG6HV 0xb0005007
+#define MASK_TH_VLSEG6HV 0xfdf0707f
+#define MATCH_TH_VLSEG6WV 0xb0006007
+#define MASK_TH_VLSEG6WV 0xfdf0707f
+#define MATCH_TH_VLSEG7BV 0xd0000007
+#define MASK_TH_VLSEG7BV 0xfdf0707f
+#define MATCH_TH_VLSEG7HV 0xd0005007
+#define MASK_TH_VLSEG7HV 0xfdf0707f
+#define MATCH_TH_VLSEG7WV 0xd0006007
+#define MASK_TH_VLSEG7WV 0xfdf0707f
+#define MATCH_TH_VLSEG8BV 0xf0000007
+#define MASK_TH_VLSEG8BV 0xfdf0707f
+#define MATCH_TH_VLSEG8HV 0xf0005007
+#define MASK_TH_VLSEG8HV 0xfdf0707f
+#define MATCH_TH_VLSEG8WV 0xf0006007
+#define MASK_TH_VLSEG8WV 0xfdf0707f
+#define MATCH_TH_VLSSEG2BV 0x38000007
+#define MASK_TH_VLSSEG2BV 0xfc00707f
+#define MATCH_TH_VLSSEG2HV 0x38005007
+#define MASK_TH_VLSSEG2HV 0xfc00707f
+#define MATCH_TH_VLSSEG2WV 0x38006007
+#define MASK_TH_VLSSEG2WV 0xfc00707f
+#define MATCH_TH_VLSSEG3BV 0x58000007
+#define MASK_TH_VLSSEG3BV 0xfc00707f
+#define MATCH_TH_VLSSEG3HV 0x58005007
+#define MASK_TH_VLSSEG3HV 0xfc00707f
+#define MATCH_TH_VLSSEG3WV 0x58006007
+#define MASK_TH_VLSSEG3WV 0xfc00707f
+#define MATCH_TH_VLSSEG4BV 0x78000007
+#define MASK_TH_VLSSEG4BV 0xfc00707f
+#define MATCH_TH_VLSSEG4HV 0x78005007
+#define MASK_TH_VLSSEG4HV 0xfc00707f
+#define MATCH_TH_VLSSEG4WV 0x78006007
+#define MASK_TH_VLSSEG4WV 0xfc00707f
+#define MATCH_TH_VLSSEG5BV 0x98000007
+#define MASK_TH_VLSSEG5BV 0xfc00707f
+#define MATCH_TH_VLSSEG5HV 0x98005007
+#define MASK_TH_VLSSEG5HV 0xfc00707f
+#define MATCH_TH_VLSSEG5WV 0x98006007
+#define MASK_TH_VLSSEG5WV 0xfc00707f
+#define MATCH_TH_VLSSEG6BV 0xb8000007
+#define MASK_TH_VLSSEG6BV 0xfc00707f
+#define MATCH_TH_VLSSEG6HV 0xb8005007
+#define MASK_TH_VLSSEG6HV 0xfc00707f
+#define MATCH_TH_VLSSEG6WV 0xb8006007
+#define MASK_TH_VLSSEG6WV 0xfc00707f
+#define MATCH_TH_VLSSEG7BV 0xd8000007
+#define MASK_TH_VLSSEG7BV 0xfc00707f
+#define MATCH_TH_VLSSEG7HV 0xd8005007
+#define MASK_TH_VLSSEG7HV 0xfc00707f
+#define MATCH_TH_VLSSEG7WV 0xd8006007
+#define MASK_TH_VLSSEG7WV 0xfc00707f
+#define MATCH_TH_VLSSEG8BV 0xf8000007
+#define MASK_TH_VLSSEG8BV 0xfc00707f
+#define MATCH_TH_VLSSEG8HV 0xf8005007
+#define MASK_TH_VLSSEG8HV 0xfc00707f
+#define MATCH_TH_VLSSEG8WV 0xf8006007
+#define MASK_TH_VLSSEG8WV 0xfc00707f
+#define MATCH_TH_VLXSEG2BV 0x3c000007
+#define MASK_TH_VLXSEG2BV 0xfc00707f
+#define MATCH_TH_VLXSEG2HV 0x3c005007
+#define MASK_TH_VLXSEG2HV 0xfc00707f
+#define MATCH_TH_VLXSEG2WV 0x3c006007
+#define MASK_TH_VLXSEG2WV 0xfc00707f
+#define MATCH_TH_VLXSEG3BV 0x5c000007
+#define MASK_TH_VLXSEG3BV 0xfc00707f
+#define MATCH_TH_VLXSEG3HV 0x5c005007
+#define MASK_TH_VLXSEG3HV 0xfc00707f
+#define MATCH_TH_VLXSEG3WV 0x5c006007
+#define MASK_TH_VLXSEG3WV 0xfc00707f
+#define MATCH_TH_VLXSEG4BV 0x7c000007
+#define MASK_TH_VLXSEG4BV 0xfc00707f
+#define MATCH_TH_VLXSEG4HV 0x7c005007
+#define MASK_TH_VLXSEG4HV 0xfc00707f
+#define MATCH_TH_VLXSEG4WV 0x7c006007
+#define MASK_TH_VLXSEG4WV 0xfc00707f
+#define MATCH_TH_VLXSEG5BV 0x9c000007
+#define MASK_TH_VLXSEG5BV 0xfc00707f
+#define MATCH_TH_VLXSEG5HV 0x9c005007
+#define MASK_TH_VLXSEG5HV 0xfc00707f
+#define MATCH_TH_VLXSEG5WV 0x9c006007
+#define MASK_TH_VLXSEG5WV 0xfc00707f
+#define MATCH_TH_VLXSEG6BV 0xbc000007
+#define MASK_TH_VLXSEG6BV 0xfc00707f
+#define MATCH_TH_VLXSEG6HV 0xbc005007
+#define MASK_TH_VLXSEG6HV 0xfc00707f
+#define MATCH_TH_VLXSEG6WV 0xbc006007
+#define MASK_TH_VLXSEG6WV 0xfc00707f
+#define MATCH_TH_VLXSEG7BV 0xdc000007
+#define MASK_TH_VLXSEG7BV 0xfc00707f
+#define MATCH_TH_VLXSEG7HV 0xdc005007
+#define MASK_TH_VLXSEG7HV 0xfc00707f
+#define MATCH_TH_VLXSEG7WV 0xdc006007
+#define MASK_TH_VLXSEG7WV 0xfc00707f
+#define MATCH_TH_VLXSEG8BV 0xfc000007
+#define MASK_TH_VLXSEG8BV 0xfc00707f
+#define MATCH_TH_VLXSEG8HV 0xfc005007
+#define MASK_TH_VLXSEG8HV 0xfc00707f
+#define MATCH_TH_VLXSEG8WV 0xfc006007
+#define MASK_TH_VLXSEG8WV 0xfc00707f
+#define MATCH_TH_VLSEG2BFFV 0x31000007
+#define MASK_TH_VLSEG2BFFV 0xfdf0707f
+#define MATCH_TH_VLSEG2HFFV 0x31005007
+#define MASK_TH_VLSEG2HFFV 0xfdf0707f
+#define MATCH_TH_VLSEG2WFFV 0x31006007
+#define MASK_TH_VLSEG2WFFV 0xfdf0707f
+#define MATCH_TH_VLSEG3BFFV 0x51000007
+#define MASK_TH_VLSEG3BFFV 0xfdf0707f
+#define MATCH_TH_VLSEG3HFFV 0x51005007
+#define MASK_TH_VLSEG3HFFV 0xfdf0707f
+#define MATCH_TH_VLSEG3WFFV 0x51006007
+#define MASK_TH_VLSEG3WFFV 0xfdf0707f
+#define MATCH_TH_VLSEG4BFFV 0x71000007
+#define MASK_TH_VLSEG4BFFV 0xfdf0707f
+#define MATCH_TH_VLSEG4HFFV 0x71005007
+#define MASK_TH_VLSEG4HFFV 0xfdf0707f
+#define MATCH_TH_VLSEG4WFFV 0x71006007
+#define MASK_TH_VLSEG4WFFV 0xfdf0707f
+#define MATCH_TH_VLSEG5BFFV 0x91000007
+#define MASK_TH_VLSEG5BFFV 0xfdf0707f
+#define MATCH_TH_VLSEG5HFFV 0x91005007
+#define MASK_TH_VLSEG5HFFV 0xfdf0707f
+#define MATCH_TH_VLSEG5WFFV 0x91006007
+#define MASK_TH_VLSEG5WFFV 0xfdf0707f
+#define MATCH_TH_VLSEG6BFFV 0xb1000007
+#define MASK_TH_VLSEG6BFFV 0xfdf0707f
+#define MATCH_TH_VLSEG6HFFV 0xb1005007
+#define MASK_TH_VLSEG6HFFV 0xfdf0707f
+#define MATCH_TH_VLSEG6WFFV 0xb1006007
+#define MASK_TH_VLSEG6WFFV 0xfdf0707f
+#define MATCH_TH_VLSEG7BFFV 0xd1000007
+#define MASK_TH_VLSEG7BFFV 0xfdf0707f
+#define MATCH_TH_VLSEG7HFFV 0xd1005007
+#define MASK_TH_VLSEG7HFFV 0xfdf0707f
+#define MATCH_TH_VLSEG7WFFV 0xd1006007
+#define MASK_TH_VLSEG7WFFV 0xfdf0707f
+#define MATCH_TH_VLSEG8BFFV 0xf1000007
+#define MASK_TH_VLSEG8BFFV 0xfdf0707f
+#define MATCH_TH_VLSEG8HFFV 0xf1005007
+#define MASK_TH_VLSEG8HFFV 0xfdf0707f
+#define MATCH_TH_VLSEG8WFFV 0xf1006007
+#define MASK_TH_VLSEG8WFFV 0xfdf0707f
+
 /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */
 #define MATCH_VT_MASKC 0x607b
 #define MASK_VT_MASKC 0xfe00707f