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authorYoshinori Sato <ysato@users.sourceforge.jp>2018-12-25 20:44:15 +0900
committerYoshinori Sato <ysato@users.sourceforge.jp>2019-01-05 22:49:46 +0900
commit59581069b4d070ab0ac61047177ee119110d678e (patch)
treeb3f11a584caa2a4b2a14ddcca94ead2bdac32d94 /include/opcode/rx.h
parent2eab46b176fa315ebc07569280f020c3348c2aa2 (diff)
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RX: include - Add RXv3 support.
* elf/rx.h (EF_RX_CPU_MASK): Update new bits. (E_FLAG_RX_V3): New RXv3 type. * opcode/rx.h (RX_Size): Add double size. (RX_Operand_Type): Add double FPU registers. (RX_Opcode_ID): Add new instuctions.
Diffstat (limited to 'include/opcode/rx.h')
-rw-r--r--include/opcode/rx.h32
1 files changed, 32 insertions, 0 deletions
diff --git a/include/opcode/rx.h b/include/opcode/rx.h
index a1519ae..8b27fe5 100644
--- a/include/opcode/rx.h
+++ b/include/opcode/rx.h
@@ -38,6 +38,7 @@ typedef enum
RX_SWord,
RX_3Byte,
RX_Long,
+ RX_Double,
RX_Bad_Size,
RX_MAX_SIZE
} RX_Size;
@@ -54,6 +55,11 @@ typedef enum
RX_Operand_Condition, /* eq, gtu, etc */
RX_Operand_Flag, /* [UIOSZC] */
RX_Operand_TwoReg, /* [Rn + scale*R2] */
+ RX_Operand_DoubleReg, /* DRn */
+ RX_Operand_DoubleRegH,/* DRHn */
+ RX_Operand_DoubleRegL,/* DRLn */
+ RX_Operand_DoubleCReg,/* DCRxx */
+ RX_Operand_DoubleCond,/* UN/EQ/LE/LT */
} RX_Operand_Type;
typedef enum
@@ -180,6 +186,32 @@ typedef enum
RXO_racl,
RXO_rdacl,
RXO_rdacw,
+
+ RXO_bfmov,
+ RXO_bfmovz,
+ RXO_rstr,
+ RXO_save,
+ RXO_dmov,
+ RXO_dpopm,
+ RXO_dpushm,
+ RXO_mvfdc,
+ RXO_mvfdr,
+ RXO_mvtdc,
+ RXO_dabs,
+ RXO_dadd,
+ RXO_dcmp,
+ RXO_ddiv,
+ RXO_dmul,
+ RXO_dneg,
+ RXO_dround,
+ RXO_dsqrt,
+ RXO_dsub,
+ RXO_dtoi,
+ RXO_dtof,
+ RXO_dtou,
+ RXO_ftod,
+ RXO_itod,
+ RXO_utod
} RX_Opcode_ID;
/* Condition bitpatterns, as registers. */