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| author | Jin Ma <jinma@linux.alibaba.com> | 2023-11-18 15:06:31 +0800 |
|---|---|---|
| committer | Nelson Chu <nelson@rivosinc.com> | 2023-11-23 09:31:48 +0800 |
| commit | 4d8f1ff3bc75dde16f52513de77c7b22a0650f7a (patch) | |
| tree | 1e5788add88865a05c582a39e3aa4c28904965ca /include/opcode/riscv-opc.h | |
| parent | 763c4daa35a9f98533d91309917ae70d51893064 (diff) | |
| download | fsf-binutils-gdb-4d8f1ff3bc75dde16f52513de77c7b22a0650f7a.zip fsf-binutils-gdb-4d8f1ff3bc75dde16f52513de77c7b22a0650f7a.tar.gz fsf-binutils-gdb-4d8f1ff3bc75dde16f52513de77c7b22a0650f7a.tar.bz2 | |
RISC-V: Add sub-extension XTheadZvamo for T-Head VECTOR vendor extension
T-Head has a range of vendor-specific instructions. Therefore
it makes sense to group them into smaller chunks in form of
vendor extensions.
This patch adds the sub-extension "XTheadZvamo" for the
"XTheadVector" extension, and it provides AMO instructions
for T-Head VECTOR vendor extension. The 'th' prefix and the
"XTheadVector" extension are documented in a PR for the
RISC-V toolchain conventions ([1]).
[1] https://github.com/riscv-non-isa/riscv-toolchain-conventions/pull/19
Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): Add support
for "XTheadZvamo" extension.
(riscv_multi_subset_supports_ext): Likewise.
gas/ChangeLog:
* doc/c-riscv.texi:
* testsuite/gas/riscv/x-thead-vector-zvamo.d: New test.
* testsuite/gas/riscv/x-thead-vector-zvamo.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_TH_VAMOADDWV): New.
* opcode/riscv.h (enum riscv_insn_class): Add insn class.
opcodes/ChangeLog:
* riscv-opc.c: Likewise.
Diffstat (limited to 'include/opcode/riscv-opc.h')
| -rw-r--r-- | include/opcode/riscv-opc.h | 37 |
1 files changed, 36 insertions, 1 deletions
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index 6556de2..58618a4 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2849,7 +2849,42 @@ #define MASK_TH_VLSEG8HFFV 0xfdf0707f #define MATCH_TH_VLSEG8WFFV 0xf1006007 #define MASK_TH_VLSEG8WFFV 0xfdf0707f - +#define MATCH_TH_VAMOADDWV 0x0000602f +#define MASK_TH_VAMOADDWV 0xf800707f +#define MATCH_TH_VAMOADDDV 0x0000702f +#define MASK_TH_VAMOADDDV 0xf800707f +#define MATCH_TH_VAMOSWAPWV 0x0800602f +#define MASK_TH_VAMOSWAPWV 0xf800707f +#define MATCH_TH_VAMOSWAPDV 0x0800702f +#define MASK_TH_VAMOSWAPDV 0xf800707f +#define MATCH_TH_VAMOXORWV 0x2000602f +#define MASK_TH_VAMOXORWV 0xf800707f +#define MATCH_TH_VAMOXORDV 0x2000702f +#define MASK_TH_VAMOXORDV 0xf800707f +#define MATCH_TH_VAMOANDWV 0x6000602f +#define MASK_TH_VAMOANDWV 0xf800707f +#define MATCH_TH_VAMOANDDV 0x6000702f +#define MASK_TH_VAMOANDDV 0xf800707f +#define MATCH_TH_VAMOORWV 0x4000602f +#define MASK_TH_VAMOORWV 0xf800707f +#define MATCH_TH_VAMOORDV 0x4000702f +#define MASK_TH_VAMOORDV 0xf800707f +#define MATCH_TH_VAMOMINWV 0x8000602f +#define MASK_TH_VAMOMINWV 0xf800707f +#define MATCH_TH_VAMOMINDV 0x8000702f +#define MASK_TH_VAMOMINDV 0xf800707f +#define MATCH_TH_VAMOMAXWV 0xa000602f +#define MASK_TH_VAMOMAXWV 0xf800707f +#define MATCH_TH_VAMOMAXDV 0xa000702f +#define MASK_TH_VAMOMAXDV 0xf800707f +#define MATCH_TH_VAMOMINUWV 0xc000602f +#define MASK_TH_VAMOMINUWV 0xf800707f +#define MATCH_TH_VAMOMINUDV 0xc000702f +#define MASK_TH_VAMOMINUDV 0xf800707f +#define MATCH_TH_VAMOMAXUWV 0xe000602f +#define MASK_TH_VAMOMAXUWV 0xf800707f +#define MATCH_TH_VAMOMAXUDV 0xe000702f +#define MASK_TH_VAMOMAXUDV 0xf800707f /* Vendor-specific (Ventana Microsystems) XVentanaCondOps instructions */ #define MATCH_VT_MASKC 0x607b #define MASK_VT_MASKC 0xfe00707f |